Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 25)

Altera Corporation 2–11
HardCopy II Clock Uncertainty Calculator User Guide
Launching the HardCopy II Clock Uncertainty Calculator
1 If the clock uncertainty values exceed 500 ps, they will be
highlighted on the spreadsheet. The values provided are based
on the general design’s maximum clock uncertainty. You must
verify whether the clock uncertainty causes the timing closure
for the design. Redesign may be necessary if you must reduce
the clock uncertainty number to close timing.
Using the clock uncertainty or advanced clock uncertainty calculators
depends on the design’s timing requirement, the PLL structures, or both.
Create Clock Uncertainty Timing Constraints on a SDC
After you have the clock transfer report and clock uncertainty values, you
can start to create the clock uncertainty constraints file in SDC format. Use
the TimeQuest Timing Analyzer SDC File Editor to create a constraint
file.
Use the following syntax to set the clock uncertainty value:
set_clock_uncertainty [-fall_from <fall_from_clock>] [-fall_to
<fall_to_clock>] [-from <from_clock>] [-hold] [-rise_from
<rise_from_clock>] [-rise_to <rise_to_clock>] [-setup] [-to <to_clock>]
<uncertainty>
Refer to the highlighted column in Figure 2–12 of the clock transfer report
and clock uncertainty values for the following procedures:
1. From the clock transfer report, identify the transfer clock type of the
pair of source and destination clocks.
For example, from altpll0:PLL0|altpll"altpll_component|_clk0
(source clock) to altpll0:PLL0|altpll"altpll_component|_clk1
(destination clock), the trasfer clock type is Intra-Clock Transfer.
2. From the clock transfer report, identify the cell type of both source
and destination clock pins.
For example, both altpll0:PLL0|altpll"altpll_component|_clk0
(source clock) and altpll0:PLL0|altpll"altpll_component|_clk1
(destination clock) are the PLL's output clock pins.
3. Based on the step 1 and 2 information, refer to the clock uncertainty
values to collect both setup and hold uncertainty values.
For example, Intra-Clock Transfer and with PLL: Setup CU = 100 ps,
Hold CU = 50 ps.