Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 62)

A–30 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide
I/O Interface with Cascaded PLLs
Figure A–31 shows an example of a clock-pair = CLK6 to Off-chip
Figure A–31. Output Interface with Cascaded PLLs
Table A–31 shows input of the PLL index for Figure A–31 , with respect to
the source and destination clocks.
PLL10 PLL2
INBUF
DATA
Source
Clock
Source
Register
CLK5 CLK2
Table A–31. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
10 2 0 —