Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 47
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A–15
HardCopy II Clock Uncertainty Calculator User Guide
shows an example of a clock-pair = CLK6 to CLK7
Figure A–16. Intra-Clock Domain with Cascaded PLLs and 2 PLL Outputs
shows input of the PLL index for
, with respect to
the source and destination clocks.
INBUF
PLL9
PLL11
CLK6
CLK7
Source
Clock
Destination
Clock
Source
Register
Destination
Register
CLK5
Table A–16. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
9
11
9
11
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