Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 56
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A–24
Altera
Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
shows an example of a clock-pair = CLK9 to CLK7
Figure A–25. Inter-Clock Domain with Two Independent Clocks and Cascaded PLLs on the Destination Clock
shows input of the PLL index for
, with respect to
the source and destination clocks.
INBUF2
PLL11
Source
Clock
Source
Register
Destination
Register
CLK5
CLK7
PLL10
INBUF4
Destination
Clock
CLK9
Table A–25. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
0
—
10
11
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