Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 51
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A–19
HardCopy II Clock Uncertainty Calculator User Guide
shows an example of a clock-pair= CLK7 to CLK8
Figure A–20. Inter-Clock Domain with Cascaded PLLs and One PLL Shared and the Second PLL on the
Source Clock
shows input of the PLL index for
, with respect to
the source and destination clocks.
INBUF
CLK5
CLK8
Source
Clock
Destination
Clock
Source
Register
Destination
Register
PLL3
PLL2
CLK7
Table A–20. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
3
2
3
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