Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 53
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A–21
HardCopy II Clock Uncertainty Calculator User Guide
shows an example of a clock-pair = CLK7 to CLK10
Figure A–22. Inter-Clock Domain with Cascaded PLLs on the Source Clock and One PLL on the Destination
Clock
shows input of the PLL index for
, with respect to
the source and destination clocks.
INBUF
Source
Clock
Destination
Clock
Source
Register
Destination
Register
PLL4
PLL11
CLK2
CLK10
CLK5
PLL6
CLK7
Table A–22. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
4
6
11
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