Inter-clock domain with cascaded plls – Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 48
Advertising
A–16
Altera
Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
Inter-Clock
Domain with
Cascaded PLLs
This section provides clock transfer examples for an inter-clock domain
with cascaded PLLs.
shows an example of a clock-pair = CLK7 to CLK9
Figure A–17. Inter-Clock Domain with Cascaded PLLs on Destination Clock
shows input of the PLL index for
, with respect to
the source and destination clocks.
INBUF
PLL3
PLL5
CLK7
CLK9
Source
Clock
Destination
Clock
Source
Register
Destination
Register
CLK2
Table A–17. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
0
—
3
5
Advertising