Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 60
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A–28
Altera
Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
shows an example of a clock-pair = CLK11 to CLK6
Figure A–29. Inter-Clock Domain with Two Independent Clocks and Cascaded PLLs on Both Source and
Destination Clocks
shows input of the PLL index for
, with respect to
the source and destination clocks.
PLL5
PLL9
INBUF3
Source
Clock
Source
Register
Destination
Register
CLK10
CLK11
PLL4
PLL3
INBUF4
Destination
Clock
CLK5
CLK6
Table A–29. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
5
9
4
3
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