Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 54
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A–22
Altera
Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
shows an example of a clock-pair = CLK3 to CLK6
Figure A–23. Inter-Clock Domain with Cascaded PLLs and One Shared and One on Source Clock and One on
Destination Clock
shows input of the PLL index for
, with respect to
the source and destination clocks.
INBUF
PLL12
CLK3
CLK6
Source
Clock
Destination
Clock
Source
Register
Destination
Register
CLK2
CLK5
PLL3
PLL7
Table A–23. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
12
3
12
7
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