Altera HardCopy II Clock Uncertainty Calculator - Manual (Page 50)

A–18 Altera Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
Figure A–19 shows an example of a clock-pair = CLK5 to CLK7
Figure A–19. Inter-Clock Domain with Cascaded PLLs and One PLL Shared and the Second PLL on the
Destination Clock
Table A–19 shows input of the PLL index for Figure A–19 , with respect to
the source and destination clocks.
INBUF
PLL7 PLL9
CLK5
CLK7
Source
Clock
Destination
Clock
Source
Register
Destination
Register
CLK4
Table A–19. Location of Input PLLs
Source Clock Destination Clock
1st PLL 2nd PLL 1st PLL 2nd PLL
7 — 7 9