Altera HardCopy II Clock Uncertainty Calculator User Manual
Page 58
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A–26
Altera
Corporation
HardCopy II Clock Uncertainty Calculator User Guide
Inter-Clock Domain with Cascaded PLLs
shows an example of a clock-pair = CLK2 to CLK10
Figure A–27. Inter-Clock Domain with Two Independent Clocks and Cascaded PLLs on the Destination Clock
and One PLL on the Source Clock
shows input of the PLL index for
, with respect to
the source and destination clocks.
PLL10
INBUF6
PLL8
Source
Clock
Source
Register
Destination
Register
CLK9
CLK10
PLL4
INBUF3
Destination
Clock
CLK2
Table A–27. Location of Input PLLs
Source Clock
Destination Clock
1st PLL
2nd PLL
1st PLL
2nd PLL
10
—
4
8
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