Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition - Manual (Page 21)

Chapter 2: Board Components 2–13
MAX II CPLD System Controller
May 2014 Altera Corporation Transceiver Signal Integrity Development Kit
Stratix V GT Edition Reference Manual
PWR_GOOD J1 — —
Power good signal to indicate that all voltage rails
have come up to their proper levels.
RESETN T2 — 2.5-V FPGA reset LED
S5_RSTN T15 AV19 2.5-V FPGA reset
S5_SMBCLK_TEMP D3 B8 2.5-V Temperature monitor SMB clock
S5_SMBDATA_TEMP C2 A8 2.5-V Temperature monitor SMB data
SCL_OSC D8 — 2.5-V Configuration clock oscillator
SCL_PM C8 L11 2.5-V Configuration clock power monitor
SDA_OSC B7 — 2.5-V Configuration data oscillator
SDA_PM A6 M11 2.5-V Configuration data power monitor
SPARE0 A10 AH19 2.5-V Spare signals to the MAX II CPLD
SPARE1 A9 AG19 2.5-V Spare signals to the MAX II CPLD
SPARE2 A8 AJ18 2.5-V Spare signals to the MAX II CPLD
SPARE3 A7 AH18 2.5-V Spare signals to the MAX II CPLD
SPARE4 B11 AN19 2.5-V Spare signals to the MAX II CPLD
SPARE5 B10 AM19 2.5-V Spare signals to the MAX II CPLD
SPARE6 B9 AR19 2.5-V Spare signals to the MAX II CPLD
SPARE7 B8 AP19 2.5-V Spare signals to the MAX II CPLD
USB_MAX_D0 M3 — 2.5-V USB configuration data bus
USB_MAX_D1 L4 — 2.5-V USB configuration data bus
USB_MAX_D2 N1 — 2.5-V USB configuration data bus
USB_MAX_D3 L3 — 2.5-V USB configuration data bus
USB_MAX_D4 N2 — 2.5-V USB configuration data bus
USB_MAX_D5 M4 — 2.5-V USB configuration data bus
USB_MAX_D6 N3 — 2.5-V USB configuration data bus
USB_MAX_D7 P2 — 2.5-V USB configuration data bus
USB_MAX_PWR_ENn E1 — 2.5-V USB configuration power enable
USB_MAX_RDn D1 — 2.5-V USB configuration read from FIFO
USB_MAX_RXFn F4 — 2.5-V USB configuration receive enable
USB_MAX_TXEn E2 — 2.5-V USB configuration transmit enable
USB_MAX_WR F3 — 2.5-V USB configuration write to FIFO
USER_IMAGE R7 — 2.5-V User image for configuration
Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 5 of 5)
Schematic Signal
Name
MAX II CPLD
Pin Number
Stratix V GT
Pin Number
I/O
Standard
Description