Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition - Manual (Page 6)

1–2 Chapter 1: Overview
Board Component Blocks
Transceiver Signal Integrity Development Kit May 2014 Altera Corporation
Stratix V GT Edition Reference Manual
■ FPGA configuration circuitry
■ MAX ® II CPLD (EPM2210F256C3N) and flash Fast Passive Parallel (FPP)
configuration
■ MAX II CPLD (EPM570M100C4N) for on-board USB-Blaster TM to use with the
Quartus ® II Programmer
■ JTAG header for external USB-Blaster
■ Flash storage for two configuration images (factory and user)
■ On-Board clocking circuitry
■ 625-MHz, 644.53125-MHz, 706.25-MHz, and 875-MHz programmable
oscillators for the high-speed transceiver reference clocks
■ 25/100/125/200 MHz jumper-selectable oscillator to the FPGA
■ 50-MHz general-purpose oscillator to the FPGA
■ One differential SMA clock input to the FPGA
■ Four differential SMA clock input to the transceivers
■ Spread spectrum clock input
■ Four clock trigger outputs
■ Transceiver interfaces
■ Four 28-Gbps TX/RX channels to MMPX connectors (for Stratix V GT FPGA
only)
■ Seven 12.5-Gbps TX/RX channels to SMA connectors
■ One 12.5-Gbps TX/RX channel to SFP+ cage
■ One 12.5-Gbps TX/RX channel to XFP cage
■ Seven 12.5-Gbps TX/RX channels to Molex backplane connectors
■ Seven 12.5-Gbps TX/RX channels to Amphenol backplane connectors
■ Seven 12.5-Gbps TX/RX channels to Tyco backplane connectors
■ Memory devices
■ One 1-Gbit (Gb) synchronous flash with a 16-bit data bus
■ Communication ports
■ USB type-B connector
■ Gigabit Ethernet port and RJ-45 jack
■ LCD header
■ General user I/O
■ Eight user LEDs
■ Three configuration status LEDs (factory, user, error)
■ Six Ethernet LEDs
■ One 16-character × 2-line character LCD display