Configuration, status, and setup elements, Configuration, Fpga programming over embedded usb-blaster – Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition User Manual
Page 22: Configuration, status, and setup elements –14, Configuration –14, Fpga programming over embedded usb-blaster –14
2–14
Chapter 2: Board Components
Configuration, Status, and Setup Elements
Transceiver Signal Integrity Development Kit
May 2014
Altera Corporation
Stratix V GT Edition Reference Manual
lists the MAX II CPLD System Controller component reference and
manufacturing information.
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD System Controller
device programming methods supported by the Stratix V GT transceiver signal
integrity development board.
The Stratix V GT transceiver signal integrity development board supports three
configuration methods:
■
Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■
MAX II and flash FPP download for configuring the FPGA using stored images
from the flash on either power-up or pressing the reset push-button (S5).
■
JTAG header (J93) for initial debugging and to bring up the on-board USB-Blaster
circuitry.
FPGA Programming over Embedded USB-Blaster
Programming the FPGA over embedded USB-Blaster is implemented using a type-B
USB connector (CN1), a USB 2.0 PHY device, and an Altera MAX II CPLD
EPM2210F256C3N (U19). This allows configuration of the FPGA using a USB cable
that connects directly between the USB port on the board (CN1) and a USB port of a
PC running the Quartus II software. The embedded USB-Blaster in the MAX II CPLD
System Controller acts as a master to the JTAG chain.
A green USB-Blaster LED (D8) indicates the USB-Blaster activity. The embedded
USB-Blaster is automatically disabled when you connect an external USB-Blaster to
the JTAG chain at the JTAG header (J93).
Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board Reference
Description
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U19
MAX II CPLD 256FBGA -3 LF
3.3 V VCCINT
Altera
Corporation
EPM2210F256C3N