National Instruments AT-MIO-16X - Manual (Page 123)

Chapter 4 Register Map and Descriptions
© National Instruments Corporation 4-27 AT-MIO-16X User Manual
until cleared by strobing the DMATCB
Clear Register.
9 OVERFLOW Overflow—This bit indicates whether
the ADC FIFO has overflowed during a
sample run. OVERFLOW is an error
condition that occurs if the FIFO fills up
with A/D conversion data and A/D
conversions continue. If OVERFLOW is
set, A/D conversion data has been lost
because of FIFO overflow. If
OVERFLOW is clear, no overflow has
occurred. If OVERFLOW occurs during
a data acquisition operation, the data
acquisition is terminated immediately.
This bit is reset by strobing the DAQ
Clear Register.
8 OVERRUN Overrun—This bit indicates whether an
A/D conversion was initiated before the
previous A/D conversion was complete.
OVERRUN is an error condition that can
occur if the data acquisition sample
interval is too small (sample rate is too
high). If OVERRUN is set, one or more
conversions were skipped. If OVERRUN
is clear, no overrun condition has
occurred. If OVERRUN occurs during a
data acquisition operation, the data
acquisition is immediately terminated.
This bit is reset by strobing the DAQ
Clear Register.
7 TMRREQ Timer Request—This bit reflects the
status of the timer update. TMRREQ is
set whenever the DAC FIFO is ready to
receive data, or a pulse has occurred on
the TMRTRIG* signal in the interrupt
mode. TMRREQ generates an interrupt
or DMA request only if the proper mode
is selected according to Table 4-3. In
DMA transfer mode, TMRREQ is
automatically cleared when the DAC is
written to. In interrupt and programmed