Adc fifo register, Adc fifo register -32 – National Instruments AT-MIO-16X User Manual

Page 128

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Chapter 4

Register Map and Descriptions

AT-MIO-16X User Manual

4-32

© National Instruments Corporation

ADC FIFO Register

Reading the ADC FIFO Register returns the oldest ADC conversion
value stored in the ADC FIFO. Whenever the ADC FIFO is read, the
value read is removed from the ADC FIFO, thereby leaving space for
another ADC conversion value to be stored. Values are shifted into the
ADC FIFO whenever an ADC conversion is complete.

The ADC FIFO is emptied when all values it contains are read. Status
Register 1 should be read to determine the FIFO state before the ADC
FIFO Register is read. If the ADC FIFO contains one or more ADC
conversion values, the ADCFIFOEF* bit is set in Status Register 1
and the ADC FIFO Register can be read to retrieve a value. If the
ADCFIFOEF* bit is cleared, the ADC FIFO is empty, in which case
reading the ADC FIFO Register returns meaningless information. If the
ADCFIFOHF* flag is clear in Status Register 1, the ADC FIFO is at
least half-full with conversion data, and 256 FIFO values can be read
without checking the ADCFIFOEF* in Status Register 1.

The values returned by reading the ADC FIFO Register are available in
two different binary formats: straight binary, which generates only
positive numbers, or two’s complement binary, which generates both
positive and negative numbers. The binary format used is determined by
the mode in which the ADC is configured. The bit pattern returned for
either format is given as follows:

Address:

Base address + 00 (hex)

Type:

Read-only

Word Size:

16-bit

Bit Map:

Bit

Name

Description

15-0

D<15..0>

Local data bus bits. When the ADC FIFO
is addressed, these bits are the result of a
16-bit ADC conversion. Values read
range from 0 to 65,535 decimal (0x0000
to 0xFFFF) when the ADC is in unipolar
mode, and –32,768 to 32,767 decimal

15

D15

14

D14

13

D13

12

D12

11

D11

10

D10

9

D9

8

D8

7

D7

6

D6

5

D5

4

D4

3

D3

2

D2

1

D1

0

D0

LSB

MSB

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