Document Outline

• NI 6124/6154 User Manual
• Support
  • Worldwide Technical Support and Product Information
  • National Instruments Corporate Headquarters
  • Worldwide Offices
• Important Information
  • Warranty
  • Copyright
  • Trademarks
  • Patents
  • WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS
• Compliance
• Contents
• About This Manual
  • Conventions
  • Related Documentation
• Chapter 1 Getting Started
  • Installing NI-DAQmx
  • Installing Other Software
  • Installing the Hardware
  • Device Self-Calibration
  • Device Pinouts
  • Device Specifications
• Chapter 2 DAQ System Overview
  • Figure 2-1. Typical DAQ System
  • DAQ Hardware
    • Figure 2-2. General NI 6124 Block Diagram
    • Figure 2-3. General NI 6154 Block Diagram
    • DAQ-STC2
  • Calibration Circuitry
    • Internal or Self-Calibration
    • External Calibration
  • Signal Conditioning
  • Sensors and Transducers
  • Programming Devices in Software
• Chapter 3 I/O Connector
  • NI 6124 I/O Connector Signal Descriptions
    • Table 3-1. NI 6124 Device Signal Descriptions
  • NI 6154 I/O Connector Signal Descriptions
    • Table 3-2. NI 6154 I/O Connector Signal Descriptions
  • +5 V Power Source
• Chapter 4 Analog Input
  • Figure 4-1. Non-Isolated S Series Analog Input Block Diagram
  • Figure 4-2. Isolated S Series Analog Input Block Diagram
  • Analog Input Terminal Configuration
  • Input Polarity and Range
  • Working Voltage Range
  • AI Data Acquisition Methods
  • Analog Input Triggering
  • Connecting Analog Input Signals
    • Table 4-1. S Series Analog Input Signal Configuration
    • Types of Signal Sources
    • Differential Connections for Ground-Referenced Signal Sources
      • Figure 4-3. Differential Connection for Ground-Referenced Signals on Non-Isolated Devices
      • Figure 4-4. Differential Connection for Ground-Referenced Signals on Isolated Devices
      • Common-Mode Signal Rejection Considerations
    • Differential Connections for Non-Referenced or Floating Signal Sources
      • Figure 4-5. Differential Connection for Non-Referenced Signals on Non-Isolated Devices
      • Figure 4-6. Differential Connection for Non-Referenced Signals on Isolated Devices
      • DC-Coupled
      • AC-Coupled
    • Field Wiring Considerations
    • Minimizing Drift in Differential Mode
  • Analog Input Timing Signals
    • Figure 4-7. Typical Posttriggered DAQ Sequence
    • Figure 4-8. Typical Pretriggered DAQ Sequence
    • AI Sample Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Routing AI Sample Clock Signal to an Output Terminal
      • Other Timing Requirements
      • Figure 4-9. AI Sample Clock and AI Start Trigger
    • AI Sample Clock Timebase Signal
    • AI Convert Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Routing AI Convert Clock Signal to an Output Terminal
    • AI Convert Clock Timebase Signal
    • AI Hold Complete Event Signal
    • AI Start Trigger Signal
      • Using a Digital Source
      • Using an Analog Source
      • Routing AI Start Trigger to an Output Terminal
    • AI Reference Trigger Signal
      • Figure 4-10. Reference Trigger Final Buffer
      • Using a Digital Source
      • Using an Analog Source
      • Routing AI Reference Trigger Signal to an Output Terminal
  • Getting Started with AI Applications in Software
• Chapter 5 Analog Output
  • Figure 5-1. Non-Isolated S Series Device Analog Output Block Diagram
  • Figure 5-2. Isolated S Series Device Analog Output Block Diagram
  • Minimizing Glitches on the Output Signal
  • AO Data Generation Methods
  • Analog Output Triggering
  • Connecting Analog Output Signals
    • Figure 5-3. Analog Output Connections for Non-Isolated S Series Devices
    • Figure 5-4. Analog Output Connections for Isolated S Series Devices
  • Waveform Generation Timing Signals
    • Figure 5-5. Analog Output Engine Routing Options
    • AO Sample Clock Signal
      • Using an Internal Source
      • Using an External Source
      • Figure 5-6. AO Sample Clock Timing Requirements
      • Routing AO Sample Clock Signal to an Output Terminal
      • Other Timing Requirements
      • Figure 5-7. AO Sample Clock and AO Start Trigger
    • AO Sample Clock Timebase Signal
      • Figure 5-8. AO Sample Clock Timebase Timing Requirements
    • AO Start Trigger Signal
      • Using a Digital Source
      • Figure 5-9. AO Start Trigger Timing Requirements
      • Using an Analog Source
      • Routing AO Start Trigger Signal to an Output Terminal
    • AO Pause Trigger Signal
      • Using a Digital Source
      • Using an Analog Source
  • Getting Started with AO Applications in Software
• Chapter 6 Digital I/O
  • Digital I/O for Non-Isolated Devices
    • Figure 6-1. Non-Isolated S Series Digital I/O Circuitry
    • Static DIO for Non-Isolated Devices
    • Digital Waveform Triggering for Non-Isolated Devices
      • Figure 6-2. Digital Waveform Triggering
    • Digital Waveform Acquisition for Non-Isolated Devices
      • DI Sample Clock Signal
    • Digital Waveform Generation for Non-Isolated Devices
      • DO Sample Clock Signal
    • I/O Protection for Non-Isolated Devices
    • Programmable Power-Up States for Non-Isolated Devices
    • DI Change Detection for Non-Isolated Devices
      • Figure 6-3. DI Change Detection
      • DI Change Detection Applications for Non-Isolated Devices
    • Connecting Digital I/O Signals on Non-Isolated Devices
      • Figure 6-4. Digital I/O Connections
    • Getting Started with DIO Applications in Software on Non-Isolated Devices
  • Digital I/O for Isolated Devices
    • Figure 6-5. Isolated S Series Devices Digital I/O Block Diagram
    • Static DIO for Isolated Devices
    • I/O Protection for Isolated Devices
    • Connecting Digital I/O Signals on Isolated Devices
      • Figure 6-6. Isolated S Series Device Digital I/O Signal Connections
    • Getting Started with DIO Applications in Software on Isolated Devices
• Chapter 7 Counters
  • Figure 7-1. S Series Counters
  • Counter Input Applications
    • Counting Edges
      • Single Point (On-Demand) Edge Counting
      • Figure 7-2. Single Point (On-Demand) Edge Counting
      • Figure 7-3. Single Point (On-Demand) Edge Counting with Pause Trigger
      • Buffered (Sample Clock) Edge Counting
      • Figure 7-4. Buffered (Sample Clock) Edge Counting
      • Controlling the Direction of Counting
    • Pulse-Width Measurement
      • Single Pulse-Width Measurement
      • Figure 7-5. Single Pulse-Width Measurement
      • Buffered Pulse-Width Measurement
      • Figure 7-6. Buffered Pulse-Width Measurement
    • Period Measurement
      • Single Period Measurement
      • Figure 7-7. Single Period Measurement
      • Buffered Period Measurement
      • Figure 7-8. Buffered Period Measurement
    • Semi-Period Measurement
      • Single Semi-Period Measurement
      • Buffered Semi-Period Measurement
      • Figure 7-9. Buffered Semi-Period Measurement
    • Frequency Measurement
      • Figure 7-10. Method 1
      • Figure 7-11. Method 1b
      • Figure 7-12. Method 2
      • Figure 7-13. Method 3
      • Choosing a Method for Measuring Frequency
      • Table 7-1. Frequency Measurement Method 1
      • Table 7-2. Frequency Measurement Method Comparison
    • Position Measurement
      • Measurements Using Quadrature Encoders
      • Figure 7-14. X1 Encoding
      • Figure 7-15. X2 Encoding
      • Figure 7-16. X4 Encoding
      • Figure 7-17. Channel Z Reload with X4 Decoding
      • Measurements Using Two Pulse Encoders
      • Figure 7-18. Measurements Using Two Pulse Encoders
      • Buffered (Sample Clock) Position Measurement
      • Figure 7-19. Buffered Position Measurement
    • Two-Signal Edge-Separation Measurement
      • Single Two-Signal Edge-Separation Measurement
      • Figure 7-20. Single Two-Signal Edge-Separation Measurement
      • Buffered Two-Signal Edge-Separation Measurement
      • Figure 7-21. Buffered Two-Signal Edge-Separation Measurement
  • Counter Output Applications
    • Simple Pulse Generation
      • Single Pulse Generation
      • Figure 7-22. Single Pulse Generation
      • Single Pulse Generation with Start Trigger
      • Figure 7-23. Single Pulse Generation with Start Trigger
      • Retriggerable Single Pulse Generation
      • Figure 7-24. Retriggerable Single Pulse Generation
    • Pulse Train Generation
      • Continuous Pulse Train Generation
      • Figure 7-25. Continuous Pulse Train Generation
      • Finite Pulse Train Generation
      • Figure 7-26. Finite Pulse Train Timing Diagram
    • Frequency Generation
      • Using the Frequency Generator
      • Figure 7-27. Frequency Generator Block Diagram
      • Figure 7-28. Frequency Generator Output Waveform
    • Frequency Division
    • Pulse Generation for ETS
      • Figure 7-29. Pulse Generation for ETS
  • Counter Timing Signals
    • Counter n Source Signal
      • Table 7-3. Counter Applications and Counter n Source
      • Routing a Signal to Counter n Source
      • Routing Counter n Source to an Output Terminal
    • Counter n Gate Signal
      • Routing a Signal to Counter n Gate
      • Routing Counter n Gate to an Output Terminal
    • Counter n Aux Signal
      • Routing a Signal to Counter n Aux
    • Counter n A, Counter n B, and Counter n Z Signals
      • Routing Signals to A, B, and Z Counter Inputs
      • Routing Counter n Z Signal to an Output Terminal
    • Counter n Up_Down Signal
    • Counter n HW Arm Signal
      • Routing Signals to Counter n HW Arm Input
    • Counter n Internal Output and Counter n TC Signals
      • Routing Counter n Internal Output to an Output Terminal
    • Frequency Output Signal
      • Routing Frequency Output to a Terminal
  • Default Counter/Timer Pinouts
  • Counter Triggering
  • Other Counter Features
    • Cascading Counters
    • Counter Filters
      • Table 7-4. Filters
      • Figure 7-30. Filter Example
    • Prescaling
      • Figure 7-31. Prescaling
    • Duplicate Count Prevention
      • Example Application That Works Correctly (No Duplicate Counting)
      • Figure 7-32. Duplicate Count Prevention Example
      • Example Application That Works Incorrectly (Duplicate Counting)
      • Figure 7-33. Duplicate Count Example
      • Example Application That Prevents Duplicate Count
      • Figure 7-34. Duplicate Count Prevention Example
      • When To Use Duplicate Count Prevention
      • Enabling Duplicate Count Prevention in NI-DAQmx
    • Synchronization Modes
      • Table 7-5. Synchronization Mode Conditions
      • 80 MHz Source Mode
      • Figure 7-35. 80 MHz Source Mode
      • Other Internal Source Mode
      • Figure 7-36. Other Internal Source Mode
      • External Source Mode
      • Figure 7-37. External Source Mode
• Chapter 8 Programmable Function Interfaces (PFI)
  • PFI for Non-Isolated Devices
    • Figure 8-1. PFI Circuitry on Non-Isolated S Series Devices
  • PFI for Isolated Devices
    • Figure 8-2. PFI Input Circuitry on Isolated S Series Devices
    • Figure 8-3. PFI Output Circuitry on Isolated S Series Devices
  • Using PFI Terminals as Timing Input Signals
  • Exporting Timing Output Signals Using PFI Terminals
  • Using PFI Terminals as Static Digital Inputs and Outputs
  • Connecting PFI Input Signals
    • Figure 8-4. PFI Input Signals Connections
  • PFI Filters
    • Table 8-1. Filters
    • Figure 8-5. Filter Example
  • I/O Protection
  • Programmable Power-Up States
• Chapter 9 Digital Routing and Clock Generation
  • Clock Routing
    • Figure 9-1. S Series Clock Routing Circuitry
    • 80 MHz Timebase
    • 20 MHz Timebase
    • 100 kHz Timebase
    • External Reference Clock
    • 10 MHz Reference Clock
  • Synchronizing Multiple Devices
  • Real-Time System Integration (RTSI)
    • RTSI Connector Pinout
      • Table 9-1. RTSI Signals
      • Figure 9-2. S Series PCI Device RTSI Pinout
    • Using RTSI as Outputs
    • Using RTSI Terminals as Timing Input Signals
    • RTSI Filters
      • Table 9-2. Filters
      • Figure 9-3. Filter Example
  • PXI Clock and Trigger Signals
    • PXI_CLK10
    • PXI Triggers
    • PXI_STAR Trigger
    • PXI_STAR Filters
      • Table 9-3. Filters
      • Figure 9-4. Filter Example
  • Routing Signals in Software
    • Table 9-4. Signal Routing in Software
• Chapter 10 Bus Interface
  • MITE and DAQ-PnP
  • PXI Considerations
    • PXI Clock and Trigger Signals
    • PXI Express
  • Data Transfer Methods
    • Changing Data Transfer Methods between DMA and IRQ
• Chapter 11 Triggering
  • Triggering with a Digital Source
    • Figure 11-1. Falling-Edge Trigger
  • Triggering with an Analog Source
    • Figure 11-2. Analog Trigger Circuitry
    • Analog Input Channel
    • Analog Trigger Actions
  • Analog Trigger Types
    • Figure 11-3. Below-Level Analog Triggering Mode
    • Figure 11-4. Above-Level Analog Triggering Mode
    • Figure 11-5. Analog Edge Triggering with Hysteresis Rising Slope Example
    • Figure 11-6. Analog Edge Triggering with Hysteresis Falling Slope Example
    • Figure 11-7. Analog Window Triggering Mode (Entering Window)
  • Analog Trigger Accuracy
• Appendix A Device-Specific Information
  • Figure A-1. NI 6124 Pinout
  • Table A-1. Default NI-DAQmx Counter/Timer Pins
  • Figure A-2. NI 6124 Block Diagram
  • Figure A-3. NI 6154 Pinout
  • Table A-2. NI 6154 Device Default NI-DAQmx Counter/Timer Pins
  • Figure A-4. NI 6154 Block Diagram
  • Table A-3. Ground Symbols
• Appendix B Technical Support and Professional Services
• Glossary
  • Symbols
  • A
  • B-C
  • D
  • E-F
  • G-L
  • M-P
  • Q-R
  • S-T
  • V
• Index
  • Numerics
  • A
  • B-C
  • D
  • E-F
  • G-M
  • N-P
  • Q-S
  • T
  • U-X