Rockwell Automation 1770-KF2 Data Highway or Highway Plus Interface Module User Manual - Manual (Page 57)

Asynchronous Link Protocols
Chapter 4
4-14
If a DLE STX is received, the BCC and the message buffer are reset; and
the receiver starts building a message.
While building a message, all data codes are stored in the message buffer
and added to the BCC. If the buffer overflows, the receiver continues
summing the BCC, but the data is discarded. If a parity, overrun, framing,
or modem handshaking error is detected, it is recorded. If any control
codes other than a DLE EXT BCC are received, the message is aborted
and a DLE NAK sent on Path 2. When the DLE ETX BCC is received,
the error flag, the BCC, the message size, and the address (optionally) are
all checked. If any of the tests fail, a DLE NAK is sent on Path 2.
If the message is OK, its header is compared to the last message. If it is
the same, the message is discarded; and a DLE ACK is sent. (Duplicate
message detection is not implemented if Switch 1 of Switch Group SW-1
is turned off.)
If the message is different from the last one, the state of the message sink
is tested. If the message sink is full, a DLE NAK is sent; otherwise the
message is forwarded to the message sink; the header information is saved
for the duplicate message detector; and a DLE ACK is sent.
The procedure for the 1771-KC/KD and 1771-KG (Revision C) modules
is different. First, they check the message sink state. If the sink is full,
the response is recorded but not sent. The receiver waits for a DLE ENQ
on Path 1. If any other code is received, the response is changed from
ACK to NAK and the receiver continues waiting for a DLE ENQ. If a
DLE ENQ is received, the sink status is checked. If it is still full, the
receiver continues waiting. If it is not full, the last response is sent; and
the receiver then accepts new messages. This variation is not documented
in the structured English section found in Table 4.B.
The receiver for the KF2 module is listed in Table 4.B in structured
English. Figure 4.8 is a flowchart of the software logic for implementing
the receiver.