ADLINK PXES-2590 - Manual (Page 26)

16 Introduction
ing local bus line can transmit analog or digital signals between
modules.
Trigger Bus
The trigger bus is an 8-line bus that connects all slots on the
PXES-2590, providing inter-module synchronization. PXI and
PXI Express modules can exchange trigger or clock signals
through the trigger bus, allowing precisely timed response to
asynchronous external events the system is monitoring or con-
trolling.
Reference Clock
The PXES-2590 backplane supplies single-ended 10MHz ref-
erence clock (PXI_CLK10) and differential 100MHz clock
(PXIe_CLK100) to each peripheral slot for inter-module syn-
chronization. The independent buffers drive the clock signal to
each peripheral slot.
These common reference clock signals can synchronize multi-
ple modules in a PXI Express chassis. PXI modules with
phase-lock loop circuits can lock reference clocks to generate
an in-phase timebase.
The PXI_CLK10 and PXIe_CLK100 clocks are in-phase
according to the PXI-5 specification. Since the external 10MHz
clock input can override the onboard 10MHz clock source, a
phase-lock loop (PLL) circuit on the backplane synchronizes
the PXIe_CLK100 and external 10MHz clock. Three LED indi-
cators on the left side of the system controller slot indicate sta-
tus as follows.