Spectrum Controls 1734sc-OE2CIH - Manual (Page 65)

Chapter 4: OE2CIH and HART 4-29
User’s Manual Pub. 0300272-01 Rev. A.0
Reply Data
Get Single Channel Device - Reply packet structure
Reply Size = 12 or (12*n)
Offset Field Value Definition
0 Communication Established 0×00
(1 byte)–
Not
established
0×01
(1 byte)–
Established Indicates presence of HART
device
1 HART Comm/Cmd Response
Status byte (1 byte) HART Communication Status
byte (First Status byte from
device)
2 HART Field Device Status
byte (1 byte) HART field device Status byte
(Second Status byte from device)
3 Manufacturer ID/EDTMSB (1 byte) CMD#0, Byte 1
4 Device Type/EDTLSB (1 byte) CMD#0, Byte 2
5-7 Device ID (3 bytes) HART Device ID (MSB first)
8-9 Manufacturer ID 16 Bit (2 bytes) CMD#0, Byte 1 if HART rev
less than 7
CMD#0, Bytes 17 to 18 if HART
rev greater than or equal to 7
10-11 ExpandedDeviceTypeCode (2 bytes) CMD#0, Byte 2 if HART Rev
less than 7
CMD#0, Bytes 1 to 2 if HART
Rev greater than or equal to 7
12 to
(12*n) Above 12 bytes repeated for
all Channels
Ramp Rate
The module uses a fixed ramp rate per channel of 100 ms full-scale. This prevents
introducing unnecessary noise during HART communications while the outputs are
commanded to large deltas.
Inter Processor Communications
Main Processor Detects Error
This module contains multiple MCUs; the main application processor, and two HART
modem processors. If, at any time, the communications between any of these processors
is disrupted for more than one (1) second, the channel enters a hard fault state. Since the
state of the HART processor is unknown, and it has direct control over the DAC, the
HART processor is held in reset. It remains in this state until power is cycled.
The Module Status LED is set to blinking red and the Channel Status LED is set to solid
red.
The module status bit is set to Major Unrecoverable Fault. The entire byte of status is
set to 0×FF to indicate a hard fault on the channel.