Cache line size, Cache, Line size – Avago Technologies LSI53C876E User Manual
Page 101: Cache line, Size, Class code, Revision id, 0x08, 0x0c, Register: 0x08
PCI Configuration Registers
4-7
Register: 0x08
Revision ID
Read Only
RID
Revision ID
[7:0]
This field specifies device and revision identifiers. The
value of this register is 0x00110111 or 0x37.
Register: 0x09
Class Code
Read Only
CC
Class Code
[23:0]
This register is used to identify the generic function of the
device. The upper byte of this register is a base class
code, the middle byte is a subclass code, and the lower
byte identifies a specific register level programming
interface. The value of this register is 0x010000, which
identifies a SCSI controller.
Register: 0x0C
Cache Line Size
Read/Write
CLS
Cache Line Size
[7:0]
This register specifies the system cache line size in units
of 32-bit words. The value in this register is used by the
device to determine whether to use Write and Invalidate
or Write commands for performing write cycles, and
whether to use Read, Read Line, or Read Multiple
7
0
RID
0
0
1
1
0
1
1
1
23
0
CC
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
CLS
0
0
0
0
0
0
0
0