Avago Technologies LSI53C876E - Manual (Page 13)

Contents xiii
6.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/,
TESTIN, DIFFSENS
6-3
6.6 Capacitance 6-4
6.7 Output Signals—INTA/, INTB/ 6-4
6.8 Output Signals—SDIR[15:0], SDIRP0, SDIRP1, BSYDIR,
SELDIR, RSTDIR, TGS, IGS, MAS/[1:0], MCE/,
MOE/_TESTOUT, MWE/
6-4
6.9 Output Signal—REQ/ 6-5
6.10 Output Signal—SERR/ 6-5
6.11 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR
6-5
6.12 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
6-6
6.13 Bidirectional Signals—MAD[7:0] 6-6
6.14 Input Signals—TDI, TMS, TCK 6-6
6.15 Output Signal—TDO 6-7
6.16 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR
6-7
6.17 Input Signals—CLK, GNT/, IDSEL, RST/, 6-7
6.18 Output Signals—INTA/, INTB, REQ/ 6-8
6.19 Output Signal—SERR/ 6-8
6.20 TolerANT Technology Electrical Characteristics 6-9
6.21 Clock Timing 6-12
6.22 Reset Input 6-13
6.23 Interrupt Output 6-14
6.24 3.3 V PCI Timing 6-16
6.25 Configuration Register Read 6-17
6.26 Configuration Register Write 6-18
6.27 Target Read (Not From External Memory) 6-19
6.28 Target Write (Not From External Memory) 6-20
6.29 Target Read (From External Memory) 6-21
6.30 Target Write (From External Memory) 6-25
6.31 Opcode Fetch, Nonburst 6-28
6.32 Opcode Fetch, Burst 6-30
6.33 Back-to-Back Read 6-32
6.34 Back-to-Back Write 6-34
6.35 Burst Read 6-37
6.36 Burst Write 6-41