Avago Technologies LSI53C876E - Manual (Page 71)

Power Management 2-49
in the Power State D2 section. The PCI Function Power States D0, D1,
D2, and D3 are described below. Power state actions are separate for
each function.
2.5.1 Power State D0
Power state D0 is the maximum power state and is the power-up default
state for each function.
2.5.2 Power State D1
Power state D1 is a lower power state than D0. In this state, the
LSI53C876 core is placed in the snooze mode and the SCSI CLK is
disabled. In the snooze mode, a SCSI reset does not generate an /IRQ
signal. However, by setting the Wakeup Interrupt Enable bit (bit 3 in the
SCSI Interrupt Enable One (SIEN1) register), then a SCSI reset
generates an /IRQ signal, but SCSI CLK is still disabled.
2.5.3 Power State D2
Power state D2 is a lower power state than D1. In this state, the
LSI53C876 core is placed in the coma mode. The following PCI
Configuration Space command register enable bits are suppressed:
•
I/O Space Enable
•
Memory Space Enable
•
Bus Mastering Enable
•
SERR
•
PERR
Thus, the memory and I/O spaces cannot be accessed, and the
LSI53C876 cannot be a PCI bus master. Furthermore, SCSI and DMA
interrupts are disabled when in power state D2. If changed from power
state D2 to power state D1 or D0, the previous values of the PCI
Command register are restored. Also, any pending interrupts before the
function entered power state D2 are asserted.