Table 6.33 back-to-back read, Back-to-back read – Avago Technologies LSI53C876E User Manual
Page 264
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6-32
Electrical Characteristics
Table 6.33
Back-to-Back Read
Symbol
Parameter
1
1. See note on page 6-16 regarding 3.3 V PCI Timing Changes.
Min
Max
Unit
t
1
Shared signal input setup time
7
–
ns
t
2
Shared signal input hold time
0
–
ns
t
3
CLK to shared signal output valid
–
11
ns
t
4
Side signal input setup time
10
–
ns
t
5
Side signal input hold time
0
–
ns
t
6
CLK to side signal output valid
–
12
ns
t
9
CLK high to MASTER/ low
–
20
ns
t
10
CLK high to MASTER/ high
–
20
ns
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