Avago Technologies LSI53C876E User Manual
Page 178
4-84
Registers
SEL
Selection Time-Out
[3:0]
These bits select the SCSI selection/reselection time-out
period. When this timing (plus the 200
µ
s selection abort
time) is exceeded, the STO bit in the
register is set. For a more detailed
explanation of interrupts, refer to
HTH[7:4]
SEL[3:0]
GEN[3:0]
1
Minimum Time-out
(80 MHz Clock) With
Scale Factor Bit
Cleared
Minimum Time-out
(80 MHz Clock)
With Scale Factor
Bit Set
0000
Disabled
Disabled
0001
100
µ
s
1.6 ms
0010
200
µ
s
3.2 ms
0011
400
µ
s
6.4 ms
0100
800
µ
s
12.8 ms
0101
.6 ms
25.6 ms
0110
3.2 ms
51.2 ms
0111
6.4 ms
102.4 ms
1000
12.8 ms
204.8 ms
1001
25.6 ms
409.6 ms
1010
51.2 ms
819.2 ms
1011
102.4 ms
1.6 s
1100
204.8 ms
3.2 s
1101
409.6 ms
6.4 s
1110
19.2 ms
12.8 s
1111
1.6+ s
25.6 s
1. These values are correct if the CCF bits in the
register are set according to the valid
combinations in the bit description.