Avago Technologies LSI53C876E - Manual (Page 262)

6-30 Electrical Characteristics
Table 6.32 Opcode Fetch, Burst
Symbol Parameter
1
1. See note on page 6-16 regarding 3.3 V PCI Timing Changes.
Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
t
4
Side signal input setup time 10 – ns
t
5
Side signal input hold time 0 – ns
t
6
CLK to side signal output valid – 12 ns
t
7
CLK high to FETCH/ low – 20 ns
t
8
CLK high to FETCH/ high – 20 ns
t
9
CLK high to MASTER/ low – 20 ns
t
10
CLK high to MASTER/ high – 20 ns