Document Outline

• CONTROLLER MANUAL
• FR60
  • 32-BIT MICROCONTROLLER
• MB91460 Series
  • User’s Manual
  • Version 1.00
  • 2006-10-22
  • - PRELIMINARY -
• FR60
  • 32-BIT MICROCONTROLLER
• MB91460 Series
  • User’s Manual
• Chapter 1 Introduction
  • 1. How to Handle the Device
    • To set latch-up prevention
    • Termination of unused pin
    • Power-supply pin
    • Crystal-oscillator circuit
    • NC and OPEN pin termination
    • Mode pins (from MD0 to MD2)
    • At the time of power-on
    • Source oscillation input at the time of power-on
    • Caution: during the PLL clock operation
    • For more specification about operating voltage, see the latest data sheet.
  • 2. Instruction for Users
  • 3. Caution: debug-related matters
  • 4. How to Use This Document
• Chapter 2 MB91460 Rev.A/Rev.B Overview
  • 1. Overview
  • 2. Features
    • 2.1 FR60 CPU Core
    • 2.2 Instruction Cache
    • 2.3 Interrupt Controller
    • 2.4 Internal Data RAM
    • 2.5 Internal Instruction/Data RAM
    • 2.6 Embedded Instruction/Data Memory
    • 2.7 External Bus Interface
    • 2.8 DMA Controller
    • 2.9 Infotainment extension (MB91460 Rev.B)
    • 2.10 Peripheral Function
  • 3. MB91460 Series Product Lineup
  • 4. Block Diagram
• Chapter 3 MB91460 Series Basic Information
  • 1. Memory Map
  • 2. I/O Map
  • 3. Interrupt Vector Table
  • 4. Package
  • 5. Pin Assignment Diagram
  • 6. Pin Definitions
  • 7. I/O Circuit Type
  • 8. Pin State Table
• Chapter 4 CPU Architecture
  • 1. Overview
  • 2. Features
  • 3. CPU
  • 4. 32-bit/16-bit Bus Converter
  • 5. Harvard/Princeton Bus Converter
  • 6. Instruction Overview
  • 7. Data Structure
  • 8. Word Alignment
  • 9. Addressing
• Chapter 5 CPU Registers
  • 1. General-purpose Registers
  • 2. Dedicated Registers
    • 2.1 PC: Program Counter
    • 2.2 PS: Program Status Register
    • 2.3 TBR: Table-base Register
    • 2.4 RP: Return Pointer
    • 2.5 SSP: System Stack Pointer
    • 2.6 USP: User Stack Pointer
    • 2.7 MDH, MDL: Multiply & Divide Register
• Chapter 6 EIT: Exceptions, Interrupts and Traps
  • 1. Overview
  • 2. Features
  • 3. EIT Trigger
  • 4. Return from EIT
  • 5. EIT Interrupt Level
  • 6. EIT Vector Table
  • 7. Multiple EIT Processing
  • 8. Operation
    • 8.1 User Interrupt operation
    • 8.2 Operation of INT Instruction
    • 8.3 Operation of INTE Instruction
    • 8.4 Operation of Step Trace Trap
    • 8.5 Operation of Undefined-instruction Exception
    • 8.6 Coprocessor Absent Trap
    • 8.7 Coprocessor Error Trap
    • 8.8 Operation of RETI Instruction
  • 9. Caution
• Chapter 7 Branch Instruction
  • 1. Branch Instruction with Delay Slot
  • 2. Operation of Branch Instruction with Delay Slot
  • 3. Actual Example (with Delay Slot)
    • 3.1 JMP:D @Ri / CALL:D @Ri Instruction
    • 3.2 RET:D Instruction
    • 3.3 Bcc:D rel Instruction
    • 3.4 CALL:D Instruction
  • 4. Restrictions on Branch Instruction with Delay Slot
    • 4.1 Available Instructions for Delay Slot
    • 4.2 Step Trace Trap
    • 4.3 Interrupt
    • 4.4 Undefined-instruction Exception
  • 5. Branch Instruction without Delay Slot
  • 6. Operation of Branch Instruction without Delay Slot
• Chapter 8 Device State Transition
  • 1. Overview
  • 2. Features
  • 3. State Transition Diagram
    • 3.1 RUN (Normal Operation)
    • 3.2 SLEEP
    • 3.3 STOP
    • 3.4 Oscillation-stabilization-wait RUN
    • 3.5 Oscillation-stabilization-wait Reset
    • 3.6 Operation-initialization Reset (RST)
    • 3.7 Setting-initialization Reset (INIT)
    • 3.8 Priority of Each Request of State Transition
• Chapter 9 Reset
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 RSRR: Reset Cause Register
    • 4.2 STCR: Standby Control Register
    • 4.3 MOD: Mode Pins
    • 4.4 Mode Vector
    • 4.5 Reset Vector
    • 4.6 Device Mode Overview
  • 5. INIT Pin Input (INIT: Settings Initialization Reset)
    • 5.1 Trigger
    • 5.2 Releasing the Reset Request
    • 5.3 Flag
    • 5.4 Reset Level
    • 5.5 Initialization Triggered by INIT Pin Input (INIT)
    • 5.6 Reset Cancellation Sequence
  • 6. Watchdog Reset (INIT: Settings Initialization Reset)
    • 6.1 Trigger
    • 6.2 Releasing the Reset Request
    • 6.3 Flag
    • 6.4 Reset Level
    • 6.5 Initialization Triggered by Watchdog Reset (INIT)
    • 6.6 Reset Cancellation Sequence
  • 7. Software Reset (RST: Operation Initialization Reset)
    • 7.1 Trigger
    • 7.2 Releasing the Reset Request
    • 7.3 Flag
    • 7.4 Reset Level
    • 7.5 Items Initialized by Operation Reset (RST)
    • 7.6 Reset Cancellation Sequence
  • 8. Reset Operation Modes
    • 8.1 Normal (Asynchronous) Reset Mode
    • 8.2 Synchronous Reset Operation
  • 9. MCU Operation Mode
    • 9.1 Bus Modes and Access Modes
      • Single chip mode
      • Internal ROM, external bus mode
      • External ROM, external bus mode
  • 10. Caution
• Chapter 10 Standby
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 STCR: Standby Control Register
    • 4.2 TBCR: Timebase timer control register
  • 5. Operation
    • 5.1 Sleep Mode
    • 5.2 Stop mode
  • 6. Settings
  • 7. Q&A
    • 7.1 How do I change to sleep mode?
    • 7.2 How do I change to stop mode?
    • 7.3 How do I set pins to high impedance (Hi-z) during stop mode?
    • 7.4 How do I halt the main clock oscillation during stop mode?
    • 7.5 How do I recover from sleep mode?
    • 7.6 How do I recover from stop mode?
  • 8. Caution
• Chapter 11 Memory Controller
  • 1. Overview
  • 2. FLASH Interface
  • 3. General Purpose RAM
  • 4. Instruction Cache and Data Buffer
  • 5. Prefetch
  • 6. Fixed Mode and Reset Vectors
  • 7. Registers
    • List of FLASH-IF Registers
  • 8. Explanations of Registers
    • FLASH Interface Control Register
    • FLASH Memory Wait Timing Register (FMWT)
    • FLASH Memory Adddress Check register (FMAC)
    • Non-cacheable area definition
• Chapter 12 Instruction Cache
  • 1. General description
  • 2. Main body structure
    • Control register structure
  • 3. Operating mode conditions
    • Cache status in various operating modes
    • Cache Entry Update
  • 4. Cacheable areas in the instruction cache
  • 5. Settings for handling the I-Cache
• Chapter 13 Clock Control
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 CLKR: Clock Source Control Register
    • 4.2 DIV0R: Clock Division Setting Register 0
    • 4.3 DIV1R: Clock Division Setting Register 1
    • 4.4 CSCFG: Clock Source Configuration Register
    • 4.5 OSCCR: Oscillation Control Register
  • 5. Operation
    • 5.1 Clock Setup Sequence (Example)
    • 5.2 Halting and Restarting the Main Clock Oscillation During Subclock Mode (Example)
    • 5.3 Notes
  • 6. Settings
  • 7. Q & A
    • 7.1 How do I enable or disable clock operation?
    • 7.2 How do I select the main PLL multiplier ratio?
    • 7.3 How do I select the operating clock source?
    • 7.4 How do I set the operation clock division ratios?
    • 7.5 How do I halt the main clock in sub clock mode?
    • 7.6 How do I halt the sub clock in sub clock on RC oscillator mode?
    • 7.7 How do I halt the sub clock in main clock mode?
  • 8. Caution
• Chapter 14 PLL Interface
  • 1. Overview
  • 2. Features
  • 3. Frequency calculation
  • 4. Registers
    • 4.1 PLL Control Registers
  • 5. Recommended Settings
  • 6. Clock Auto Gear Up/Down
  • 7. Caution
• Chapter 15 CAN Clock Prescaler
  • 1. Overview
  • 2. Features
  • 3. Registers
    • 3.1 CAN Clock Control Register
• Chapter 16 Clock Supervisor
  • 1. Overview Clock Supervisor
  • 2. Clock Supervisor Register
  • 3. Block Diagram Clock Supervisor
  • 4. Operation Modes
• Chapter 17 Clock Modulator
  • 1. Overview
    • Modulation degree and frequency resolution in frequency modulation mode
  • 2. Clock Modulator Registers
    • Clock modulator registers
    • Clock Modulator Control Register (CMCR)
    • Clock modulator control register contents
    • Clock Modulation Parameter Register (CMPR)
    • Modulation parameter register contents
  • 3. Application Note
    • Recommended startup sequence for frequency modulation mode
    • Modulation parameter for frequency modulation mode
    • Recommended settings
• Chapter 18 Timebase Counter
  • 1. Overview
  • 2. Features
    • 2.1 Timebase Counter (when used to generate the oscillation stabilization wait)
    • 2.2 Events that Invoke an Oscillation Stabilization Wait
      • Wait time after a settings initialization: Invoked automatically (timebase counter)
      • Wait time after recovering from stop mode: Invoked automatically (timebase counter)
      • When recovering from abnormal state with main PLL selected
      • Wait time after power on: Provided by pin input
      • Wait time after changing from subclock to main clock: Using the main oscillation stabilization wait timer to generate this time is recommended.
      • When recovering from main clock oscillation halted: Enabling the main clock oscillation and waiting for oscillation to stabilize is required.
      • Main PLL lock wait time (for main clock operation): Using the timebase timer interrupt to generate this time is recommended.
  • 3. Configuration
  • 4. Registers
    • 4.1 STCR: Standby Control Register
    • 4.2 CLKR: Clock Source Control Register
  • 5. Operation
    • 5.1 INIT Pin Input
    • 5.2 Watchdog Reset (The specified oscillation stabilization wait time is generated automatically)
    • 5.3 Recovering from Stop Mode via an Interrupt
    • 5.4 The lock wait time for the main PLL must be generated by software.
    • 5.5 Generating an Oscillation Stabilization Wait when Changing from Subclock Mode to Main Clock Mode
    • 5.6 When Recovering from an Abnormal State with the Main PLL Selected
    • 5.7 Types of Oscillation Stabilization Wait
    • 5.8 Whether or not a Stabilization Wait is Required for Each State Transition
  • 6. Settings
  • 7. Q&A
    • 7.1 How do I setup the oscillation stabilization wait time that is generated automatically?
    • 7.2 How do I set the oscillation stabilization wait time without generating it automatically?
    • 7.3 What is the clear timing for the timebase counter?
  • 8. Caution
• Chapter 19 Timebase Timer
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 TBCR: Timebase Timer Control Register
    • 4.2 CTBR: Timebase Counter Clear Register
  • 5. Operation
    • 5.1 Timebase Timer Interrupt Example (Main PLL Lock Wait)
  • 6. Setting
  • 7. Q & A
    • 7.1 What are the types of interval time used in the timebase timer (and the timebase counter used by the timebase timer) and how to select them?
    • 7.2 What Is the count clock of the timebase counter?
    • 7.3 How to operate the timebase timer?
    • 7.4 How is the timebase timer (=timebase counter) operation stopped?
    • 7.5 How is the timebase counter (=timebase timer) cleared?
    • 7.6 How about the interrupt-associated registers?
    • 7.7 What are the interrupt types?
    • 7.8 How is an interrupt enabled?
  • 8. Caution
• Chapter 20 Software Watchdog Timer
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 RSRR: Watchdog Timer Control Register
    • 4.2 WPR: Watchdog Reset Generation Postponement Register
    • 4.3 CTBR: Timebase Counter Clear Register
  • 5. Operation
    • 5.1 Watchdog (Detecting Runaway)
    • 5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period
    • 5.3 Postponing the Generation of a Watchdog Reset
    • 5.4 Confirming that the Watchdog Reset has been Generated
    • 5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement)
    • 5.6 Stopping the Watchdog Timer
  • 6. Setting
  • 7. Q & A
    • 7.1 What are the types of watchdog interval time and how are they selected?
    • 7.2 How is the watchdog operation started (set to valid)?
    • 7.3 How can we check that the watchdog reset has been generated?
    • 7.4 How is the watchdog stopped?
    • 7.5 How do I clear the watchdog timer (1-bit counter)?
  • 8. Caution
• Chapter 21 Hardware Watchdog Timer
  • 1. Overview
    • Hardware watchdog timer
  • 2. Configuration
    • Block diagram of the hardware watchdog timer
  • 3. Register
    • 3.1 Hardware watchdog timer control and status register
    • 3.2 Hardware watchdog timer duration register
  • 4. Functions
    • Function of the hardware watchdog timer
    • Period of the hardware watchdog timer
  • 5. Caution
    • Software disabling is not possible
    • Hardware disabling is only possible on the evaluation device MB91V460
    • Postponement of reset
    • Timer stop and clear
    • During DMA transfer
    • Duration setting
    • RC clock frequency
• Chapter 22 Main Oscillation Stabilisation Timer
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 OSCRH: Control Register for the Main Clock Oscillation Stability Wait Timer
  • 5. Operation
    • 5.1 Main Clock Oscillation Stability Wait
    • 5.2 Interval Interrupt
  • 6. Setting
  • 7. Q & A
    • 7.1 What are the types of interval time (wait time) and how are they selected?
    • 7.2 How do I select the count clock?
    • 7.3 How is the main clock oscillation stability wait timer count operation enabled/ disabled?
    • 7.4 How is the main clock oscillation stability wait timer cleared?
    • 7.5 What happens with the interrupt-associated registers?
    • 7.6 What are the types of interrupt?
    • 7.7 how is an interrupt enabled?
    • 7.8 How is the main clock oscillation stability wait timer stopped counting?
  • 8. Caution
• Chapter 23 Sub Oscillation Stabilisation Timer
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 WPCRH: Sub oscillation stabilisation timer Control Register
  • 5. Operation
    • 5.1 Subclock Oscillation Stability Wait Interrupt
    • 5.2 Interval Interrupt (Clock Interrupt)
    • 5.3 Returning from the Stop Mode due to Interval Operation (Clock Interrupt)
  • 6. Setting
  • 7. Q & A
    • 7.1 What are the types of interval time (wait time) and how are they selected?
    • 7.2 How is the count clock selected?
    • 7.3 How is the sub oscillation stabilisation timer cleared?
    • 7.4 What are interrupt-associated registers?
    • 7.5 What are the types of interrupt?
    • 7.6 How is the interrupt enabled?
    • 7.7 How is the sub oscillation stabilisation timer stopped counting?
  • 8. Caution
• Chapter 24 Interrupt Control
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 ICR: Interrupt Control Register
    • 4.2 Interrupt Vector
  • 5. Operation
  • 6. Setting
  • 7. Q & A
    • 7.1 How can I set interrupt levels?
    • 7.2 How do I enable interrupts?
    • 7.3 How do I disable interrupts?
    • 7.4 How can I set an I flag?
  • 8. Caution
• Chapter 25 External Interrupt
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 ELVR: Interrupt Request Level Register
    • 4.2 EIRR: Interrupt Request Register
    • 4.3 ENIR: Interrupt Request Enable Register
  • 5. Operation
  • 6. Setting
  • 7. Q & A
    • 7.1 What are the types and setting procedures of detect levels?
    • 7.2 How do I set INT pin as the input?
    • 7.3 What interrupt registers are used?
    • 7.4 Interrupt types
    • 7.5 How do I enable, disable, and clear interrupts?
  • 8. Caution
• Chapter 26 DMA Controller
  • 1. Overview of the DMA Controller (DMAC)
    • Priority (ch.0>ch.1>ch.2>ch.3>ch.4)
    • The order can be rotated between ch.0 and ch.1.
    • DMAC start sources
    • Transfer mode
  • 2. DMA Controller (DMAC) Registers
    • 2.1 Control/Status Registers A (DMACA0 to 4)
    • 2.2 Control/Status Registers B (DMACB0 to 4)
    • 2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to 4/ DMADA0 to 4)
    • 2.4 DMAC All-Channel Control Register (DMACR)
    • 2.5 Other Functions
  • 3. DMA Controller (DMAC) Operation
    • Block/step transfer
    • Burst transfer
    • Demand transfer
    • 2-cycle transfer (normal transfer)
    • Fly-by transfer (memory --> I/O)
    • Fly-by transfer (I/O --> memory)
    • Specifying the address for a 2-cycle transfer
    • Specifying the address for a fly-by transfer
    • Transfer count
    • Transfer end
    • 3.1 Setting a Transfer Request
      • Edge detection
      • Level detection
    • 3.2 Transfer Sequence
      • Burst 2-cycle transfer
      • Burst fly-by transfer
      • Demand Transfer 2-Cycle Transfer
      • Demand transfer fly-by transfer
      • Step/block transfer 2-cycle transfer
      • Step/block transfer fly-by transfer
    • 3.3 General Aspects of DMA Transfer
      • Transfer count register reloading
      • Transfer source address register reloading
      • Transfer destination address register reloading
      • Special examples of operating mode and the reload operation
    • 3.4 Addressing Mode
    • 3.5 Data Types
    • 3.6 Transfer Count Control
    • 3.7 CPU Control
    • 3.8 Hold Arbitration
    • 3.9 Operation from Starting to End/Stopping
      • Enabling operation for all channels
      • Starting transfer
      • Starting from a temporary stop
      • Setting of temporary stopping by writing to the control register (Set independently for each channel or all channels simultaneously)
      • NMI/hold suppress level interrupt processing
      • Transfer end
      • Disabling all channels
      • Transfer stop requests from peripheral circuits
    • 3.10 DMAC Interrupt Control
    • 3.11 Channel Selection and Control
      • Fixed mode
      • Rotation mode (ch.0 to ch.1 only)
    • 3.12 Supplement on External Pin and Internal Operation Timing
      • For 2-cycle transfer
      • For fly-by (read/write) transfer
      • For burst, step, block, and demand transfers
      • For burst, step, and block transfers
      • For a demand transfer
  • 4. Operation Flowcharts
  • 5. Data Bus
  • 6. DMA External Interface
    • 6.1 Input Timing of the DREQx Pin
    • 6.2 FR30 Compatible Mode of DACK
      • 2-cycle transfer mode
      • Fly-by transfer mode
• Chapter 27 Delayed Interrupt
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 DICR: Delayed Interrupt Control Register
  • 5. Operation
  • 6. Setting
  • 7. Q & A
    • 7.1 What are interrupt-associated registers?
    • 7.2 How is the interrupt request generated/cleared?
  • 8. Caution
• Chapter 28 Bit Search
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 BSD0: 0 Detection Register / BSD1:1 Detection Register / BSDC: Changing position Detection Data Register
    • 4.2 BSRR: Detection Result Register
  • 5. Operation
    • 5.1 Zero detection
    • 5.2 One Detection
    • 5.3 Changing Position Detection
  • 6. Setting
  • 7. Q & A
    • 7.1 How is data written?
    • 7.2 How is scanning started?
    • 7.3 How is a result read?
    • 7.4 How is the previous bit search state restored?
  • 8. Caution
• Chapter 29 MPU / EDSU
  • 1. Overview
  • 2. Features
  • 3. Break Functions
    • 3.1 Instruction address break
    • 3.2 Operand address break
    • 3.3 Data value break
    • 3.4 Using operand with data break
    • 3.5 Memory Protection
    • 3.6 Break Factors
  • 4. Registers
    • 4.1 List of EDSU Registers
    • 4.2 Explanations of Registers
      • EDSU Control Register (BCTRL)
      • EDSU Status Register (BSTAT)
      • EDSU Instruction Address Capture Register (BIAC)
      • EDSU Operand Address Capture Register (BOAC)
      • EDSU Break Detection Interrupt Request Register (BIRQ)
      • EDSU Channel Configuration Register (BCR0...BCR7)
      • Break Address/Data register (BAD0...BAD31)
  • 5. Quick Reference
• Chapter 30 I/O Ports
  • 1. I/O Ports Functions
  • 2. I/O Circuit Types
    • 2.1 I/O Cell List MB91V460
    • 2.2 I/O Input Voltages (VIL/VIH)
  • 3. Port Register Settings
    • 3.1 General Rules
    • 3.2 I/O Port Block Diagram
    • 3.3 Port Input Enable
    • 3.4 Port Function Register Setup
    • 3.5 Port Input Level Selection
    • 3.6 Programmable Pull-Up/Pull Down Resistors
    • 3.7 Programmable Port Output Drive
• Chapter 31 External Bus
  • 1. Overview of the External Bus Interface
    • 1.1 Features
      • The external bus interface has the following features:
      • In each chip select area, the following functions can be set independently:
      • A different detailed timing can be set for each access timing type.
      • Fly-by transfer by DMA can be performed.
      • External bus arbitration using BRQ and BGRNT can be performed.
      • Pins that are not used by the external interface can be used as general-purpose I/O ports through settings.
    • 1.2 Block Diagram
    • 1.3 I/O Pins
      • Ordinary bus interface
      • Memory interface
      • DMA interface
    • 1.4 Register List
  • 2. External Bus Interface Registers
    • 2.1 Area Select Registers 0-7(ASR0-7)
    • 2.2 Area Configuration Registers 0-7 (ACR0-7)
      • CS area mask setting function
    • 2.3 Area Wait Register (AWR0-7)
      • Memory type A(SDRAM/FCRAM) and Memory type B(FCRAM)
    • 2.4 Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode)
    • 2.5 Memory setting register (MCRB for FCRAM auto - precharge ON mode)
    • 2.6 I/O Wait Registers for DMAC (IOWR0-3)
    • 2.7 Chip Select Enable Register (CSER)
    • 2.8 Cache Enable Register (CHER)
    • 2.9 Pin/Timing Control Register (TCR)
    • 2.10 Refresh Control Register (RCR)
  • 3. Setting Example of the Chip Select Area
    • Example of setting ASRs and ASZ3-0
  • 4. Endian and Bus Access
    • Ordinary bus interface
    • Time division I/O interface
    • SDRAM Interface
    • 4.1 Big Endian Bus Access
      • Word access (when LD/ST instruction executed)
      • 32-bit bus width
      • 16-bit bus width
      • 8-bit bus width
      • 32-bit bus width
      • 16-bit bus width
      • 8-bit bus width
    • 4.2 Little Endian Bus Access
      • Word access
      • Halfword access
      • Byte access
      • 32-bit bus width
      • 16-bit bus width
      • 8-bit bus width
      • 32-bit bus width
      • 16-bit bus width
      • 8-bit bus width
    • 4.3 Comparison of Big Endian and Little Endian External Access
  • 5. Operation of the Ordinary bus interface
    • 5.1 Basic Timing
    • 5.2 Operation of WRn + Byte Control Type
    • 5.3 Read -> Write Operation
    • 5.4 Write -> Write Operation
    • 5.5 Auto-Wait Cycle
    • 5.6 External Wait Cycle
    • 5.7 Synchronous Write Enable Output
    • 5.8 CSn Delay Setting
    • 5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting
    • 5.10 DMA Fly-By Transfer (I/O -> Memory)
    • 5.11 DMA Fly-By Transfer (Memory -> I/O)
  • 6. Burst Access Operation
  • 7. Address/data Multiplex Interface
  • 8. Prefetch Operation
    • Basic conditions for starting external access using prefetch
    • Optional clear for temporary stopping of a prefetch access
    • Unit for one prefetch access operation
    • Burst length setting and prefetch efficiency
    • Reading from the prefetch buffer
    • Clearing/updating the prefetch buffer
    • Restrictions on prefetch-enabled areas
  • 9. SDRAM/FCRAM Interface Operation
    • 9.1 Self Refresh
      • Self - refresh mode transition procedure
      • Self - refresh mode reset procedure
    • 9.2 Power-on Sequence
    • 9.3 Connecting SDRAM/FCRAM to Many Areas
    • 9.4 Address Multiplexing Format
    • 9.5 Memory Connection Example
      • Using 8 - bit SDRAM/FCRAM (Big endian)
      • Using 16 - bit SDRAM/FCRAM
      • Using 32 - bit SDRAM
  • 10. DMA Access Operation
    • 10.1 DMA Fly-By Transfer (I/O -> Memory)
    • 10.2 DMA Fly-By Transfer (Memory -> I/O)
    • 10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)
    • 10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)
      • At SDRAM page hit (Shortest)
      • At SDRAM page misses
    • 10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM)
    • 10.6 2-Cycle Transfer (External -> I/O)
    • 10.7 2-Cycle Transfer (I/O -> External)
    • 10.8 2-Cycle Transfer (I/O -> SDRAM/FCRAM)
    • 10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O)
  • 11. Bus Arbitration
  • 12. Procedure for Setting a Register
  • 13. Notes on Using the External Bus Interface
• Chapter 32 USART (LIN / FIFO)
  • 1. Overview
  • 2. USART Configuration
  • 3. USART Pins
  • 4. USART Registers
    • 4.1 Serial Control Register 04 (SCR04)
    • 4.2 Serial Mode Register 04 (SMR04)
    • 4.3 Serial Status Register 04 (SSR04)
    • 4.4 Reception and Transmission Data Register (RDR04 / TDR04)
    • 4.5 Extended Status/Control Register (ESCR04)
    • 4.6 Extended Communication Control Register (ECCR04)
    • 4.7 Baud Rate / Reload Counter Register 0 and 1 (BGR04 / 14)
    • 4.8 FIFO Control Register (FCR04)
    • 4.9 FIFO Status Register (FSR04)
  • 5. USART Interrupts
    • 5.1 Reception Interrupt Generation and Flag Set Timing
    • 5.2 Transmission Interrupt Generation and Flag Set Timing
  • 6. USART Baud Rates
    • 6.1 Setting the Baud Rate
    • 6.2 Restarting the Reload Counter
  • 7. USART Operation
    • 7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)
    • 7.2 Operation in Synchronous Mode (Operation Mode 2)
    • 7.3 Operation with LIN Function (Operation Mode 3)
    • 7.4 Direct Access to Serial Pins
    • 7.5 Bidirectional Communication Function (Normal Mode)
    • 7.6 Master-Slave Communication Function (Multiprocessor Mode)
    • 7.7 LIN Communication Function
    • 7.8 Sample Flowcharts for USART in LIN Communication (Operation Mode 3)
  • 8. Notes on using USART
• Chapter 33 I2C Controller
  • 1. Overview
  • 2. I2C Interface Registers
    • 2.1 Bus Control Register (IBCR0)
    • 2.2 Bus Status Register (IBSR0)
    • 2.3 Ten Bit Slave Address Register (ITBA0)
    • 2.4 Ten Bit Address Mask Register (ITMK0)
    • 2.5 Seven Bit Slave Address Register (ISBA0)
    • 2.6 Seven Bit Slave Address Mask Register (ISMK0)
    • 2.7 Data Register (IDAR0)
    • 2.8 Clock Control Register (ICCR0)
  • 3. I2C Interface Operation
  • 4. Programming Flow Charts
• Chapter 34 CAN Controller
  • 1. Overview
  • 2. Register Description
    • 2.1 Programmer’s Model
    • 2.2 Hardware Reset Description
    • 2.3 CAN Protocol Related Registers
    • 2.4 Message Interface Register Sets
    • 2.5 Message Object in the Message Memory
    • 2.6 Message Handler Registers
  • 3. Functional Description
    • 3.1 Software Initialisation
    • 3.2 CAN Message Transfer
    • 3.3 Disabled Automatic Retransmission
    • 3.4 Test Mode
    • 3.5 Silent Mode
    • 3.6 Loop Back Mode
    • 3.7 Loop Back combined with Silent Mode
    • 3.8 Basic Mode
    • 3.9 Software control of Pin CAN_TX
  • 4. CAN Application
    • 4.1 Management of Message Objects
    • 4.2 Message Handler State Machine
    • 4.3 Data Transfer from/to Message RAM
    • 4.4 Transmission of Messages
    • 4.5 Acceptance Filtering of Received Messages
    • 4.6 Reception of Data Frame
    • 4.7 Reception of Remote Frame
    • 4.8 Receive / Transmit Priority
    • 4.9 Configuration of a Transmit Object
    • 4.10 Updating a Transmit Object
    • 4.11 Configuration of a Receive Object
    • 4.12 Handling of Received Messages
    • 4.13 Configuration of a FIFO Buffer
    • 4.14 Reception of Messages with FIFO Buffers
    • 4.15 Reading from a FIFO Buffer
    • 4.16 Handling of Interrupts
    • 4.17 Bit Time and Bit Rate
• Chapter 35 Free-Run Timer
  • 1. Overview
  • 2. Features
  • 3. Configuration Diagram
  • 4. Registers
    • 4.1 TCCS: Timer Control Register
    • 4.2 TCDT: Timer Data Register
  • 5. Operation
    • 5.1 Count Operation of the Free-run Timer
    • 5.2 Various Clear Operations of the Free-run Timer
  • 6. Setting
  • 7. Q & A
    • 7.1 What are the types of the internal clock, and how do I select?
    • 7.2 How do I select the external clock?
    • 7.3 How do I enable / disable the count operation of the free-run timer?
    • 7.4 How do I clear the free-run timer?
    • 7.5 What interrupt registers are used?
    • 7.6 Interrupt Types
    • 7.7 How do I enable interrupts?
    • 7.8 How do I stop the free-run timer?
    • 7.9 How are the free-run timer assigned to ICU and OCU?
  • 8. Caution
• Chapter 36 Input Capture
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 IPCP: Input Capture Data Register
    • 4.2 ICS: Input Capture Control Register
  • 5. Operation
    • 5.1 Capture Timing, Interrupt Timing
    • 5.2 Input Capture Edge Specification and Operation
  • 6. Settings
  • 7. Q&A
    • 7.1 What are the varieties of active edge polarity for external input, and how do I select them?
    • 7.2 What about setting the external input pins (ICU0-7)?
    • 7.3 What about interrupt-related registers?
    • 7.4 What are the types of interrupts?
    • 7.5 How do I enable interrupts?
    • 7.6 How do I measure the pulse width of the input signal?
  • 8. Caution
• Chapter 37 Output Compare
  • 1. Overview
  • 2. Features
  • 3. Configuration Diagram
  • 4. Registers
    • 4.1 OCS: Output Control Register
    • 4.2 OCCP: Compare Register
  • 5. Operation
    • 5.1 Output Compare Output (Independent Reversal) CMODE=“0”
    • 5.2 Output Compare Output (Cooperative Reversal) CMODE=“1”
  • 6. Settings
  • 7. Q & A
    • 7.1 How do I set the compare value?
    • 7.2 How do I set the compare mode? (for OCU1, OCU3, OCU5, OCU7 output)
    • 7.3 How do I enable/disable the compare operation?
    • 7.4 How do I set the initial level of the compare pin output?
    • 7.5 How do I set the output for compare pins OCU0-OCU7?
    • 7.6 How do I clear the free-run timer?
    • 7.7 How do I enable the compare operation?
    • 7.8 How do I compare the free-run timer value with the compare register value and clear the free-run timer when they match?
    • 7.9 What are the interrupt-related registers?
    • 7.10 What are the types of interrupts?
    • 7.11 How do I enable interrupts?
    • 7.12 Compare value calculation procedure
  • 8. Caution
• Chapter 38 Reload Timer
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 TMCSR: Reload Timer Control Status Register
    • 4.2 TMR: Timer Register
    • 4.3 TMRLR: Reload register
  • 5. Operation
    • 5.1 Internal Clock/Reload Mode
    • 5.2 Internal Clock/One-shot Mode
    • 5.3 External Event Clock Reload Mode
    • 5.4 External Event Clock/One-shot Mode
    • 5.5 Operation during Reset
    • 5.6 Operation during Sleep Mode
    • 5.7 Operation during Stop Mode
    • 5.8 Operation when Returning from Stop Mode
    • 5.9 Status Transition
  • 6. Setting
  • 7. Q & A
    • 7.1 What is the reload value setting (rewriting) procedure?
    • 7.2 What are the kinds of count clocks and how are they selected?
    • 7.3 How to I enable/disable the reload timer count operation?
    • 7.4 How do I set the reload timer mode (reload/one-shot)?
    • 7.5 How do I reverse the output level?
    • 7.6 What are the kinds of triggers, and how do I select them?
    • 7.7 What are the types of external event clock active edges and how do I select them?
    • 7.8 How do I make a pin a TOT output pin?
    • 7.9 How do I make the TIN pin into an external event input pin, or an external trigger input pin?
    • 7.10 How do I generate an activation trigger?
    • 7.11 What are the interrupt-related registers?
    • 7.12 How do I enable interrupts?
    • 7.13 How do I stop the reload timer?
  • 8. Caution
• Chapter 39 Programmable Pulse Generator
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 PCSR: PPG Cycle Setting Register
    • 4.2 PDUT: PPG Duty Setting Register
    • 4.3 PCN: PPG Control Status register
    • 4.4 GCN1: General Control register 1
    • 4.5 GCN2: General Control Register 2
    • 4.6 PTMR: PPG Timer Register
  • 5. Operation
    • 5.1 PWM Operation
    • 5.2 One-Shot Operation
    • 5.3 Restart Operation
  • 6. Setting
  • 7. Q & A
    • 7.1 How do I set (rewrite) a cycle and a duty?
    • 7.2 How do I enable or disable PPG operations?
    • 7.3 How do I set the PPG operation mode (PWM operation/one-shot operation)?
    • 7.4 How do I get it restarted?
    • 7.5 What count clocks are available and how are they selected?
    • 7.6 How do I clamp the PPG pin output level?
    • 7.7 What activation triggers are available and how are they selected?
    • 7.8 How do I invert the output polarity?
    • 7.9 How do I program a pin as a PPG output pin?
    • 7.10 How do I generate an activation trigger?
    • 7.11 How do I stop a PPG operation?
    • 7.12 What interrupt registers are used?
    • 7.13 What interrupts are available and how are they selected?
    • 7.14 How do I enable, disable and clear interrupts?
  • 8. Caution
• Chapter 40 Pulse Frequency Modulator
  • 1. PFM Overview
  • 2. Reload Counter Registers
    • P0TMCSR, P1TMCSR structure
    • Functions of the P0TMCSR, P1TMCSR bits
    • P0TMR, P1TMR structure
    • P0TMRLR, P1TMRLR structure
  • 3. Reload Counter Operation
    • Counter activation and operation timing
    • Underflow operation timing
    • Counter state transitions
  • 4. PFM Operation and Setting
• Chapter 41 Up/Down Counter
  • 1. Overview
  • 2. Feature
  • 3. Configuration
  • 4. Register
    • 4.1 UDCC: Counter Control Register
    • 4.2 UDCS: Count Status Register
    • 4.3 UDCR: Up/Down Counter Register
    • 4.4 UDRC: Up/Down Reload/Compare Register
  • 5. Operation
    • 5.1 Timer Mode CMS[1:0]=“00”
    • 5.2 Up/Down Count Mode CMS[1:0]=“01”
    • 5.3 Up/Down Count Mode CMS[1:0]=“01”
    • 5.4 Phase Difference Count Mode (Multiply by 2) CMS[1:0]=“10”
    • 5.5 Phase Difference Count Mode (Multiply by 4) CMS[1:0]=“11”
    • 5.6 Clear Timing
    • 5.7 Reload Timing
    • 5.8 Writing a Value to Counter
  • 6. Setting
  • 7. Q&A
    • 7.1 How do I select a bit length (8 or 16) of Up/Down Counter?
    • 7.2 What types of count modes are available and how are they set?
    • 7.3 How do I select a count source for Up/Down Counter running in the timer mode?
    • 7.4 How do I select the edge with which Up/Down Counter running in the Up/down count mode detects an input signal (AIN or BIN)?
    • 7.5 How do I set a value to Up/Down Counter?
    • 7.6 When the Up/Down Counter's count-up value agrees with the compare value (RCR[0:1]), how do I enable clearing of Up/Down Counter the next time when the counter counts up?
    • 7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when Up/Down Counter is underflowed?
    • 7.8 How do I clear Up/Down Counter?
    • 7.9 How do I clear Up/Down Counter using the ZIN pin?
    • 7.10 How do I control Up/Down Counter's count operation using the ZIN pin?
    • 7.11 How do I enable/disable Up/Down Counter's count operation?
    • 7.12 How do I know the previous count direction (the current rotation direction)?
    • 7.13 How do I know count direction changes?
    • 7.14 How do I know that a compare-match has occurred?
    • 7.15 How do I know that an overflow or underflow has occurred?
    • 7.16 How do I set the reload/compare value?
    • 7.17 What are interrupt-related registers?
    • 7.18 What interrupts are available and how are they selected?
    • 7.19 How do I enable (select), disable or clear interrupts?
  • 8. Caution
• Chapter 42 Sound Generator
  • 1. Overview
  • 2. Block Diagram
  • 3. Registers
    • 3.1 Register Details
• Chapter 43 Stepper Motor Controller
  • 1. Overview
  • 2. Registers
    • 2.1 Registers for Stepping Motor Controller
    • 2.2 PWM Control Register
    • 2.3 PWM1&2 Compare Registers
    • 2.4 PWM1&2 Selection Registers
  • 3. Operation
  • 4. Caution
• Chapter 44 A/D Converter
  • 1. Overview of A/D Converter
  • 2. Block Diagram of A/D Converter
  • 3. Registers of A/D Converter
    • 3.1 A/D Enable Register (ADER)
    • 3.2 A/D Control Status Register (ADCS)
    • 3.3 Data Register (ADCR1, ADCR0)
    • 3.4 Sampling Timer Setting Register (ADCT)
    • 3.5 A/D Channel Setting Register (ADSCH, ADECH)
  • 4. Operation of A/D Converter
    • 4.1 Single-shot conversion mode
    • 4.2 Scan conversion mode
  • 5. Setting
  • 6. Q & A
    • 6.1 What conversion modes are available and how are they selected?
    • 6.2 How do I specify a bit length?
    • 6.3 How do I set a conversion time?
    • 6.4 How do I enable analog pin input?
    • 6.5 How do I enable analog pin input for Stepper Motor Controller?
    • 6.6 To select how to activate the A/D converter
    • 6.7 To activate the A/D converter
    • 6.8 To verify the end of a conversion
    • 6.9 How do I read a conversion value?
    • 6.10 How do I force an A/D conversion operation to a stop?
    • 6.11 What interrupt registers are used?
    • 6.12 What interrupts are available?
    • 6.13 How do I enable, disable, clear interrupts?
  • 7. Caution
• Chapter 45 D/A Converter
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 DADR: D/A Data Register
    • 4.2 DACR: D/A Control Register
  • 5. Operation
  • 6. Setting
  • 7. Q & A
    • 7.1 Where should I set digital values?
    • 7.2 How do I program the D/A pins for D/A output?
    • 7.3 How do I enable or disable D/A output?
    • 7.4 How do I activate a D/A conversion?
    • 7.5 What is the formula used to work out the value necessary to produce an expected voltage?
  • 8. Caution
• Chapter 46 Alarm Comparator
  • 1. Overview
  • 2. Block Diagram
  • 3. Alarm Comparator Control/Status Register (ACSR)
  • 4. Operation Modes
    • 4.1 Interrupt Mode (IEN=1)
    • 4.2 Polling Mode (IEN=0)
    • 4.3 Setting and Resetting of IRQ-Flagbit
    • 4.4 Power Down Modes of the Alarm Comparator
• Chapter 47 LCD Controller
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 LCR0: LCDC Control Register 0
    • 4.2 VRAM: Data Memory for Display
    • 4.3 LCR1: LCDC Control Register 1
    • 4.4 LCDCMR: Common Pin Switching Register
  • 5. Operation
    • 5.1 LCD Controller/Driver (LCDC) Operation
    • 5.2 1/2 Duty Cycle Output Waveform
    • 5.3 1/3 Duty Cycle Output Waveform
    • 5.4 1/4 Duty Cycle Output Waveform
  • 6. Setting
  • 7. Q&A
    • 7.1 How do I specify pins as COM or SEG output pins?
    • 7.2 How do I set VRM?
    • 7.3 How do I set a frame period?
    • 7.4 How do I set a duty cycle?
    • 7.5 How do I control starting and stopping of LCD?
    • 7.6 How do I enable or disable LCD display?
    • 7.7 How do I enable LCD display even in the sub-stop mode?
    • 7.8 How do I select internal or external divided resistors?
    • 7.9 How do I select internal or external divided resistors?
    • 7.10 How do I use external divided resistors to shut off the current when LCD is deactivated?
  • 8. Caution
• Chapter 48 Clock Monitor
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Register
    • 4.1 Clock Monitor Configuration Register
  • 5. Operation
  • 6. Settings
  • 7. Q&A
    • 7.1 How do I set an output terminal (MONCLK)?
    • 7.2 How do I select an output frequency?
    • 7.3 How do I enable/disable clock monitor output?
  • 8. Caution
• Chapter 49 Real-Time Clock
  • 1. Overview
  • 2. Features
  • 3. Configuration
  • 4. Registers
    • 4.1 WTCR: RTC Control Register
    • 4.2 WTBR: Sub-Second Registers
    • 4.3 WTHR/WTMR/WTSR: Hour/Minute/Second Registers
  • 5. Operation
  • 6. Setting
  • 7. Q&A
    • 7.1 How do I set the count period of 1 second?
    • 7.2 How do I initialize Real-time Clock?
    • 7.3 How do I set or update time (hour/minute/second)?
    • 7.4 How do I start or stop Real-time Clock's counting?
    • 7.5 How do I confirm that Real-time Clock is active?
    • 7.6 How do I know time?
    • 7.7 How do I stop Real-time Clock?
    • 7.8 What are interrupt-related registers?
    • 7.9 What interrupts are available and how are they selected?
    • 7.10 How do I enable interrupts?
  • 8. Caution
• Chapter 50 Subclock Calibration Unit
  • 1. Overview
    • 1.1 Description
  • 2. Block Diagram
  • 3. Timing
  • 4. Clocks
    • Clock ratio
    • The input frequencies must not exceed the values given in Table 4-1 .
  • 5. Register Description
    • 5.1 Calibration Unit Control Register (CUCR)
    • 5.2 32 kHz / 100 kHz Timer Data Register (16 bit) (CUTD)
    • 5.3 4 MHz Timer Data Register (24 bits) (CUTR)
  • 6. Application Note
    • 32kHz
    • 100kHz
• Chapter 51 Low Voltage Reset/Interrupt
  • 1. Overview
  • 2. Features
  • 3. Registers
    • 3.1 LV Detection Control Registers
• Chapter 52 Regulator Control
  • 1. Overview
  • 2. Features
  • 3. Registers
    • 3.1 Regulator Control Registers
• Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM
  • 1. Overview
  • 2. Check for Boot Conditions
    • 2.1 Evaluation Chip MB91V460
    • 2.2 Flash devices of MB91460 series (MB91F46x)
    • 2.3 Internal Bootloader Description
  • 3. Registers modified by Boot ROM
    • 3.1 Evaluation Chip MB91V460
    • 3.2 Flash devices of MB91460 series
  • 4. Flash Access Mode Switching
  • 5. Bootloader Update Strategy
• Chapter 54 Flash Memory
  • 1. Overview
  • 2. Features
  • 3. Configuration
    • 3.1 Address conversion from CPU Mode to Flash Programming Mode
  • 4. Registers
  • 5. Access Modes
    • 5.1 Access from the FR-CPU
  • 6. Flash Access Mode Switching
    • 6.1 Flash Memory Mode
  • 7. Auto Algorithms
    • 7.1 Command Operation
    • 7.2 Auto Algorithm Commands
    • 7.3 Hardware Sequence Flag
    • 7.4 FLCR: Hardware Sequence Flag
    • 7.5 Sample Use of Hardware Sequence Flag
  • 8. Caution
• Chapter 55 Flash Security
  • 1. Overview
  • 2. Features
  • 3. Flash Security Vectors
    • 3.1 Vector addresses
    • 3.2 Security Vector FSV1
    • 3.3 Security Vector FSV2
  • 4. Register
    • 4.1 Flash Security Control Register
• Chapter 56 Electrical Specification