FUJITSU MB91460 SERIES FR60 User Manual
Fr60, Preliminary
Advertising
Table of contents
Document Outline
- CONTROLLER MANUAL
- FR60
- MB91460 Series
- FR60
- MB91460 Series
- Chapter 1 Introduction
- 1. How to Handle the Device
- To set latch-up prevention
- Termination of unused pin
- Power-supply pin
- Crystal-oscillator circuit
- NC and OPEN pin termination
- Mode pins (from MD0 to MD2)
- At the time of power-on
- Source oscillation input at the time of power-on
- Caution: during the PLL clock operation
- For more specification about operating voltage, see the latest data sheet.
- 2. Instruction for Users
- 3. Caution: debug-related matters
- 4. How to Use This Document
- 1. How to Handle the Device
- Chapter 2 MB91460 Rev.A/Rev.B Overview
- Chapter 3 MB91460 Series Basic Information
- Chapter 4 CPU Architecture
- Chapter 5 CPU Registers
- Chapter 6 EIT: Exceptions, Interrupts and Traps
- Chapter 7 Branch Instruction
- Chapter 8 Device State Transition
- Chapter 9 Reset
- Chapter 10 Standby
- Chapter 11 Memory Controller
- Chapter 12 Instruction Cache
- Chapter 13 Clock Control
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Registers
- 5. Operation
- 6. Settings
- 7. Q & A
- 7.1 How do I enable or disable clock operation?
- 7.2 How do I select the main PLL multiplier ratio?
- 7.3 How do I select the operating clock source?
- 7.4 How do I set the operation clock division ratios?
- 7.5 How do I halt the main clock in sub clock mode?
- 7.6 How do I halt the sub clock in sub clock on RC oscillator mode?
- 7.7 How do I halt the sub clock in main clock mode?
- 8. Caution
- Chapter 14 PLL Interface
- Chapter 15 CAN Clock Prescaler
- Chapter 16 Clock Supervisor
- Chapter 17 Clock Modulator
- Chapter 18 Timebase Counter
- 1. Overview
- 2. Features
- 2.1 Timebase Counter (when used to generate the oscillation stabilization wait)
- 2.2 Events that Invoke an Oscillation Stabilization Wait
- Wait time after a settings initialization: Invoked automatically (timebase counter)
- Wait time after recovering from stop mode: Invoked automatically (timebase counter)
- When recovering from abnormal state with main PLL selected
- Wait time after power on: Provided by pin input
- Wait time after changing from subclock to main clock: Using the main oscillation stabilization wait timer to generate this time is recommended.
- When recovering from main clock oscillation halted: Enabling the main clock oscillation and waiting for oscillation to stabilize is required.
- Main PLL lock wait time (for main clock operation): Using the timebase timer interrupt to generate this time is recommended.
- 3. Configuration
- 4. Registers
- 5. Operation
- 5.1 INIT Pin Input
- 5.2 Watchdog Reset (The specified oscillation stabilization wait time is generated automatically)
- 5.3 Recovering from Stop Mode via an Interrupt
- 5.4 The lock wait time for the main PLL must be generated by software.
- 5.5 Generating an Oscillation Stabilization Wait when Changing from Subclock Mode to Main Clock Mode
- 5.6 When Recovering from an Abnormal State with the Main PLL Selected
- 5.7 Types of Oscillation Stabilization Wait
- 5.8 Whether or not a Stabilization Wait is Required for Each State Transition
- 6. Settings
- 7. Q&A
- 8. Caution
- Chapter 19 Timebase Timer
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Register
- 5. Operation
- 6. Setting
- 7. Q & A
- 7.1 What are the types of interval time used in the timebase timer (and the timebase counter used by the timebase timer) and how to select them?
- 7.2 What Is the count clock of the timebase counter?
- 7.3 How to operate the timebase timer?
- 7.4 How is the timebase timer (=timebase counter) operation stopped?
- 7.5 How is the timebase counter (=timebase timer) cleared?
- 7.6 How about the interrupt-associated registers?
- 7.7 What are the interrupt types?
- 7.8 How is an interrupt enabled?
- 8. Caution
- Chapter 20 Software Watchdog Timer
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Register
- 5. Operation
- 5.1 Watchdog (Detecting Runaway)
- 5.2 Starting the Watchdog Timer and Setting the Watchdog Timer Period
- 5.3 Postponing the Generation of a Watchdog Reset
- 5.4 Confirming that the Watchdog Reset has been Generated
- 5.5 Temporarily Stopped Watchdog Timer (Automatic Generation Postponement)
- 5.6 Stopping the Watchdog Timer
- 6. Setting
- 7. Q & A
- 8. Caution
- Chapter 21 Hardware Watchdog Timer
- Chapter 22 Main Oscillation Stabilisation Timer
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Register
- 5. Operation
- 6. Setting
- 7. Q & A
- 7.1 What are the types of interval time (wait time) and how are they selected?
- 7.2 How do I select the count clock?
- 7.3 How is the main clock oscillation stability wait timer count operation enabled/ disabled?
- 7.4 How is the main clock oscillation stability wait timer cleared?
- 7.5 What happens with the interrupt-associated registers?
- 7.6 What are the types of interrupt?
- 7.7 how is an interrupt enabled?
- 7.8 How is the main clock oscillation stability wait timer stopped counting?
- 8. Caution
- Chapter 23 Sub Oscillation Stabilisation Timer
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Register
- 5. Operation
- 6. Setting
- 7. Q & A
- 7.1 What are the types of interval time (wait time) and how are they selected?
- 7.2 How is the count clock selected?
- 7.3 How is the sub oscillation stabilisation timer cleared?
- 7.4 What are interrupt-associated registers?
- 7.5 What are the types of interrupt?
- 7.6 How is the interrupt enabled?
- 7.7 How is the sub oscillation stabilisation timer stopped counting?
- 8. Caution
- Chapter 24 Interrupt Control
- Chapter 25 External Interrupt
- Chapter 26 DMA Controller
- 1. Overview of the DMA Controller (DMAC)
- 2. DMA Controller (DMAC) Registers
- 3. DMA Controller (DMAC) Operation
- Block/step transfer
- Burst transfer
- Demand transfer
- 2-cycle transfer (normal transfer)
- Fly-by transfer (memory --> I/O)
- Fly-by transfer (I/O --> memory)
- Specifying the address for a 2-cycle transfer
- Specifying the address for a fly-by transfer
- Transfer count
- Transfer end
- 3.1 Setting a Transfer Request
- 3.2 Transfer Sequence
- 3.3 General Aspects of DMA Transfer
- 3.4 Addressing Mode
- 3.5 Data Types
- 3.6 Transfer Count Control
- 3.7 CPU Control
- 3.8 Hold Arbitration
- 3.9 Operation from Starting to End/Stopping
- Enabling operation for all channels
- Starting transfer
- Starting from a temporary stop
- Setting of temporary stopping by writing to the control register (Set independently for each channel or all channels simultaneously)
- NMI/hold suppress level interrupt processing
- Transfer end
- Disabling all channels
- Transfer stop requests from peripheral circuits
- 3.10 DMAC Interrupt Control
- 3.11 Channel Selection and Control
- 3.12 Supplement on External Pin and Internal Operation Timing
- 4. Operation Flowcharts
- 5. Data Bus
- 6. DMA External Interface
- Chapter 27 Delayed Interrupt
- Chapter 28 Bit Search
- Chapter 29 MPU / EDSU
- 1. Overview
- 2. Features
- 3. Break Functions
- 4. Registers
- 4.1 List of EDSU Registers
- 4.2 Explanations of Registers
- EDSU Control Register (BCTRL)
- EDSU Status Register (BSTAT)
- EDSU Instruction Address Capture Register (BIAC)
- EDSU Operand Address Capture Register (BOAC)
- EDSU Break Detection Interrupt Request Register (BIRQ)
- EDSU Channel Configuration Register (BCR0...BCR7)
- Break Address/Data register (BAD0...BAD31)
- 5. Quick Reference
- Chapter 30 I/O Ports
- Chapter 31 External Bus
- 1. Overview of the External Bus Interface
- 1.1 Features
- The external bus interface has the following features:
- In each chip select area, the following functions can be set independently:
- A different detailed timing can be set for each access timing type.
- Fly-by transfer by DMA can be performed.
- External bus arbitration using BRQ and BGRNT can be performed.
- Pins that are not used by the external interface can be used as general-purpose I/O ports through settings.
- 1.2 Block Diagram
- 1.3 I/O Pins
- 1.4 Register List
- 1.1 Features
- 2. External Bus Interface Registers
- 2.1 Area Select Registers 0-7(ASR0-7)
- 2.2 Area Configuration Registers 0-7 (ACR0-7)
- 2.3 Area Wait Register (AWR0-7)
- 2.4 Memory setting register (MCRA for SDRAM/FCRAM auto - precharge OFF mode)
- 2.5 Memory setting register (MCRB for FCRAM auto - precharge ON mode)
- 2.6 I/O Wait Registers for DMAC (IOWR0-3)
- 2.7 Chip Select Enable Register (CSER)
- 2.8 Cache Enable Register (CHER)
- 2.9 Pin/Timing Control Register (TCR)
- 2.10 Refresh Control Register (RCR)
- 3. Setting Example of the Chip Select Area
- 4. Endian and Bus Access
- 5. Operation of the Ordinary bus interface
- 5.1 Basic Timing
- 5.2 Operation of WRn + Byte Control Type
- 5.3 Read -> Write Operation
- 5.4 Write -> Write Operation
- 5.5 Auto-Wait Cycle
- 5.6 External Wait Cycle
- 5.7 Synchronous Write Enable Output
- 5.8 CSn Delay Setting
- 5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting
- 5.10 DMA Fly-By Transfer (I/O -> Memory)
- 5.11 DMA Fly-By Transfer (Memory -> I/O)
- 6. Burst Access Operation
- 7. Address/data Multiplex Interface
- 8. Prefetch Operation
- Basic conditions for starting external access using prefetch
- Optional clear for temporary stopping of a prefetch access
- Unit for one prefetch access operation
- Burst length setting and prefetch efficiency
- Reading from the prefetch buffer
- Clearing/updating the prefetch buffer
- Restrictions on prefetch-enabled areas
- 9. SDRAM/FCRAM Interface Operation
- 10. DMA Access Operation
- 10.1 DMA Fly-By Transfer (I/O -> Memory)
- 10.2 DMA Fly-By Transfer (Memory -> I/O)
- 10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)
- 10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O)
- 10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM)
- 10.6 2-Cycle Transfer (External -> I/O)
- 10.7 2-Cycle Transfer (I/O -> External)
- 10.8 2-Cycle Transfer (I/O -> SDRAM/FCRAM)
- 10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O)
- 11. Bus Arbitration
- 12. Procedure for Setting a Register
- 13. Notes on Using the External Bus Interface
- 1. Overview of the External Bus Interface
- Chapter 32 USART (LIN / FIFO)
- 1. Overview
- 2. USART Configuration
- 3. USART Pins
- 4. USART Registers
- 4.1 Serial Control Register 04 (SCR04)
- 4.2 Serial Mode Register 04 (SMR04)
- 4.3 Serial Status Register 04 (SSR04)
- 4.4 Reception and Transmission Data Register (RDR04 / TDR04)
- 4.5 Extended Status/Control Register (ESCR04)
- 4.6 Extended Communication Control Register (ECCR04)
- 4.7 Baud Rate / Reload Counter Register 0 and 1 (BGR04 / 14)
- 4.8 FIFO Control Register (FCR04)
- 4.9 FIFO Status Register (FSR04)
- 5. USART Interrupts
- 6. USART Baud Rates
- 7. USART Operation
- 7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)
- 7.2 Operation in Synchronous Mode (Operation Mode 2)
- 7.3 Operation with LIN Function (Operation Mode 3)
- 7.4 Direct Access to Serial Pins
- 7.5 Bidirectional Communication Function (Normal Mode)
- 7.6 Master-Slave Communication Function (Multiprocessor Mode)
- 7.7 LIN Communication Function
- 7.8 Sample Flowcharts for USART in LIN Communication (Operation Mode 3)
- 8. Notes on using USART
- Chapter 33 I2C Controller
- 1. Overview
- 2. I2C Interface Registers
- 2.1 Bus Control Register (IBCR0)
- 2.2 Bus Status Register (IBSR0)
- 2.3 Ten Bit Slave Address Register (ITBA0)
- 2.4 Ten Bit Address Mask Register (ITMK0)
- 2.5 Seven Bit Slave Address Register (ISBA0)
- 2.6 Seven Bit Slave Address Mask Register (ISMK0)
- 2.7 Data Register (IDAR0)
- 2.8 Clock Control Register (ICCR0)
- 3. I2C Interface Operation
- 4. Programming Flow Charts
- Chapter 34 CAN Controller
- 1. Overview
- 2. Register Description
- 3. Functional Description
- 4. CAN Application
- 4.1 Management of Message Objects
- 4.2 Message Handler State Machine
- 4.3 Data Transfer from/to Message RAM
- 4.4 Transmission of Messages
- 4.5 Acceptance Filtering of Received Messages
- 4.6 Reception of Data Frame
- 4.7 Reception of Remote Frame
- 4.8 Receive / Transmit Priority
- 4.9 Configuration of a Transmit Object
- 4.10 Updating a Transmit Object
- 4.11 Configuration of a Receive Object
- 4.12 Handling of Received Messages
- 4.13 Configuration of a FIFO Buffer
- 4.14 Reception of Messages with FIFO Buffers
- 4.15 Reading from a FIFO Buffer
- 4.16 Handling of Interrupts
- 4.17 Bit Time and Bit Rate
- Chapter 35 Free-Run Timer
- 1. Overview
- 2. Features
- 3. Configuration Diagram
- 4. Registers
- 5. Operation
- 6. Setting
- 7. Q & A
- 7.1 What are the types of the internal clock, and how do I select?
- 7.2 How do I select the external clock?
- 7.3 How do I enable / disable the count operation of the free-run timer?
- 7.4 How do I clear the free-run timer?
- 7.5 What interrupt registers are used?
- 7.6 Interrupt Types
- 7.7 How do I enable interrupts?
- 7.8 How do I stop the free-run timer?
- 7.9 How are the free-run timer assigned to ICU and OCU?
- 8. Caution
- Chapter 36 Input Capture
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Register
- 5. Operation
- 6. Settings
- 7. Q&A
- 7.1 What are the varieties of active edge polarity for external input, and how do I select them?
- 7.2 What about setting the external input pins (ICU0-7)?
- 7.3 What about interrupt-related registers?
- 7.4 What are the types of interrupts?
- 7.5 How do I enable interrupts?
- 7.6 How do I measure the pulse width of the input signal?
- 8. Caution
- Chapter 37 Output Compare
- 1. Overview
- 2. Features
- 3. Configuration Diagram
- 4. Registers
- 5. Operation
- 6. Settings
- 7. Q & A
- 7.1 How do I set the compare value?
- 7.2 How do I set the compare mode? (for OCU1, OCU3, OCU5, OCU7 output)
- 7.3 How do I enable/disable the compare operation?
- 7.4 How do I set the initial level of the compare pin output?
- 7.5 How do I set the output for compare pins OCU0-OCU7?
- 7.6 How do I clear the free-run timer?
- 7.7 How do I enable the compare operation?
- 7.8 How do I compare the free-run timer value with the compare register value and clear the free-run timer when they match?
- 7.9 What are the interrupt-related registers?
- 7.10 What are the types of interrupts?
- 7.11 How do I enable interrupts?
- 7.12 Compare value calculation procedure
- 8. Caution
- Chapter 38 Reload Timer
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Registers
- 5. Operation
- 6. Setting
- 7. Q & A
- 7.1 What is the reload value setting (rewriting) procedure?
- 7.2 What are the kinds of count clocks and how are they selected?
- 7.3 How to I enable/disable the reload timer count operation?
- 7.4 How do I set the reload timer mode (reload/one-shot)?
- 7.5 How do I reverse the output level?
- 7.6 What are the kinds of triggers, and how do I select them?
- 7.7 What are the types of external event clock active edges and how do I select them?
- 7.8 How do I make a pin a TOT output pin?
- 7.9 How do I make the TIN pin into an external event input pin, or an external trigger input pin?
- 7.10 How do I generate an activation trigger?
- 7.11 What are the interrupt-related registers?
- 7.12 How do I enable interrupts?
- 7.13 How do I stop the reload timer?
- 8. Caution
- Chapter 39 Programmable Pulse Generator
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Registers
- 5. Operation
- 6. Setting
- 7. Q & A
- 7.1 How do I set (rewrite) a cycle and a duty?
- 7.2 How do I enable or disable PPG operations?
- 7.3 How do I set the PPG operation mode (PWM operation/one-shot operation)?
- 7.4 How do I get it restarted?
- 7.5 What count clocks are available and how are they selected?
- 7.6 How do I clamp the PPG pin output level?
- 7.7 What activation triggers are available and how are they selected?
- 7.8 How do I invert the output polarity?
- 7.9 How do I program a pin as a PPG output pin?
- 7.10 How do I generate an activation trigger?
- 7.11 How do I stop a PPG operation?
- 7.12 What interrupt registers are used?
- 7.13 What interrupts are available and how are they selected?
- 7.14 How do I enable, disable and clear interrupts?
- 8. Caution
- Chapter 40 Pulse Frequency Modulator
- Chapter 41 Up/Down Counter
- 1. Overview
- 2. Feature
- 3. Configuration
- 4. Register
- 5. Operation
- 6. Setting
- 7. Q&A
- 7.1 How do I select a bit length (8 or 16) of Up/Down Counter?
- 7.2 What types of count modes are available and how are they set?
- 7.3 How do I select a count source for Up/Down Counter running in the timer mode?
- 7.4 How do I select the edge with which Up/Down Counter running in the Up/down count mode detects an input signal (AIN or BIN)?
- 7.5 How do I set a value to Up/Down Counter?
- 7.6 When the Up/Down Counter's count-up value agrees with the compare value (RCR[0:1]), how do I enable clearing of Up/Down Counter the next time when the counter counts up?
- 7.7 How do I enable reloading of the reload value (RCR[1:0]) to Up/Down Counter when Up/Down Counter is underflowed?
- 7.8 How do I clear Up/Down Counter?
- 7.9 How do I clear Up/Down Counter using the ZIN pin?
- 7.10 How do I control Up/Down Counter's count operation using the ZIN pin?
- 7.11 How do I enable/disable Up/Down Counter's count operation?
- 7.12 How do I know the previous count direction (the current rotation direction)?
- 7.13 How do I know count direction changes?
- 7.14 How do I know that a compare-match has occurred?
- 7.15 How do I know that an overflow or underflow has occurred?
- 7.16 How do I set the reload/compare value?
- 7.17 What are interrupt-related registers?
- 7.18 What interrupts are available and how are they selected?
- 7.19 How do I enable (select), disable or clear interrupts?
- 8. Caution
- Chapter 42 Sound Generator
- Chapter 43 Stepper Motor Controller
- Chapter 44 A/D Converter
- 1. Overview of A/D Converter
- 2. Block Diagram of A/D Converter
- 3. Registers of A/D Converter
- 4. Operation of A/D Converter
- 5. Setting
- 6. Q & A
- 6.1 What conversion modes are available and how are they selected?
- 6.2 How do I specify a bit length?
- 6.3 How do I set a conversion time?
- 6.4 How do I enable analog pin input?
- 6.5 How do I enable analog pin input for Stepper Motor Controller?
- 6.6 To select how to activate the A/D converter
- 6.7 To activate the A/D converter
- 6.8 To verify the end of a conversion
- 6.9 How do I read a conversion value?
- 6.10 How do I force an A/D conversion operation to a stop?
- 6.11 What interrupt registers are used?
- 6.12 What interrupts are available?
- 6.13 How do I enable, disable, clear interrupts?
- 7. Caution
- Chapter 45 D/A Converter
- Chapter 46 Alarm Comparator
- Chapter 47 LCD Controller
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Registers
- 5. Operation
- 6. Setting
- 7. Q&A
- 7.1 How do I specify pins as COM or SEG output pins?
- 7.2 How do I set VRM?
- 7.3 How do I set a frame period?
- 7.4 How do I set a duty cycle?
- 7.5 How do I control starting and stopping of LCD?
- 7.6 How do I enable or disable LCD display?
- 7.7 How do I enable LCD display even in the sub-stop mode?
- 7.8 How do I select internal or external divided resistors?
- 7.9 How do I select internal or external divided resistors?
- 7.10 How do I use external divided resistors to shut off the current when LCD is deactivated?
- 8. Caution
- Chapter 48 Clock Monitor
- Chapter 49 Real-Time Clock
- 1. Overview
- 2. Features
- 3. Configuration
- 4. Registers
- 5. Operation
- 6. Setting
- 7. Q&A
- 7.1 How do I set the count period of 1 second?
- 7.2 How do I initialize Real-time Clock?
- 7.3 How do I set or update time (hour/minute/second)?
- 7.4 How do I start or stop Real-time Clock's counting?
- 7.5 How do I confirm that Real-time Clock is active?
- 7.6 How do I know time?
- 7.7 How do I stop Real-time Clock?
- 7.8 What are interrupt-related registers?
- 7.9 What interrupts are available and how are they selected?
- 7.10 How do I enable interrupts?
- 8. Caution
- Chapter 50 Subclock Calibration Unit
- Chapter 51 Low Voltage Reset/Interrupt
- Chapter 52 Regulator Control
- Chapter 53 Fixed Mode-Reset Vector / BOOT-ROM
- Chapter 54 Flash Memory
- Chapter 55 Flash Security
- Chapter 56 Electrical Specification