FUJITSU MB91460 SERIES FR60 - Manual (Page 962)

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Chapter 48 Clock Monitor
6.Settings
6. Settings
*:For each setting procedure, refer to an appropriate section.
7. Q&A
7.1 How do I set an output terminal (MONCLK)?
Use the Clock Monitor Selection bits (CMCFG.CMSEL[3:0])
7.2 How do I select an output frequency?
Use the Output Frequency Select bit (CMCFG.CMPRE[3:0]).
7.3 How do I enable/disable clock monitor output?
Use the Output Enable bit (CMCFG.CMSEL[3:0]).
Table 6-1 Settings for Using Clock Monitor
Settings Setting Registers
Setting
Procedure*
Set a prescaler value
Clock Monitor Prescaler
(CMCFG.CMPRE[3:0])
See 7.1
Set a source clock
Clock Monitor Selection
(CMCFG.CMSEL[3:0])
See 7.1
Change the mark level
Clock Monitor Inverter
(CSCFG.MONCKI)
See 7.1
Enable clock monitor output.(MONCLK)
Clock Monitor Selection
(CMCFG.CMSEL[3:0])
See 7.2
See 7.3
Operation CMCFG.CMSEL[3:0]
To set an output terminal (MONCLK) Set to the appropriate clock (!= “0000”)
Clock Division
Ratio
Output Frequency (Example) Frequency Prescaler
(CMCFG.CMPRE[3:0]) CLKP=32MHz CLKP=40MHz
1/2 16.0 MHz 20.0 MHz Set to “0001”.
1/3 10.7 MHz 13.3 MHz Set to “0010”.
1/4 8.0 MHz 10.0 MHz Set to “0011”.
1/8 4.0 MHz 5.0 MHz Set to “0111”.
1/15 2.1 MHz 2.7 MHz Set to “1110”.
1/16 2.0 MHz 2.5 MHz Set to “1111”.
Operation Output Enable Bit (CMCFG.CMSEL[3:0])
To disable clock monitor output
(To set the terminal to the Hi-z status)
Set to “0000”.
Enable clock monitor output. Set to “0001”-”1111”.