FUJITSU MB91460 SERIES FR60 - Manual (Page 230)

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Chapter 14 PLL Interface
6.Clock Auto Gear Up/Down
this equals to (resolved closed arithmetic series of the first sum term):
with i = G ; j = G - M ; mul = MULG ; t = 1/f(pllout)
For the above given setting this equals 1483 PLL output clock cycles with a duration from the start fre-
quency to the target frequency of 9262500 ps (about 9.3 us).
duration mul t
i i 1 +
( ) i 2
+
( ) ⋅ ⋅
6
------------------------------------------ k i k – 1 +
( ) ⋅
k j 1 + =
i
∑
–
⎝ ⎠
⎜ ⎟
⎛ ⎞
⋅ ⋅
=