FUJITSU MB91460 SERIES FR60 - Manual (Page 524)

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Chapter 31 External Bus
1.Overview of the External Bus Interface
• Capable of setting timing values such as the CAS latency and RAS - CAS delay (SDRAM area)
• Capable of controlling the distributed/centralized auto - refresh, self - refresh, and other refresh timings
(SDRAM area)
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Fly-by transfer by DMA can be performed.
• Transfer between memory and I/O can be performed in a single access operation.
• The memory wait cycle can be synchronized with the I/O wait cycle in fly-by transfer.
• The hold time can be secured by only extending transfer source access.
• Idle/recovery cycles specific to fly-by transfer can be set.
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External bus arbitration using BRQ and BGRNT can be performed.
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Pins that are not used by the external interface can be used as general-purpose I/O ports through
settings.