FUJITSU MB91460 SERIES FR60 - Manual (Page 652)

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Chapter 32 USART (LIN / FIFO)
4.USART Registers
4.9 FIFO Status Register (FSR04)
Figure 4-9 Configuration of FIFO status register
(Note) The FSR04[4:0] FIFO valid data bits indicates the number of stored receptions (SVD=0) or pending
transmissions (SVD=1) in the FIFO buffer.
7 6 5 4 3 2 1 0 Initial value
0 0 0 0 0 0 0 0
B
R R R R R R R R
bit 0
FIFO valid data number
0 FIFO: number of valid Data Bit 0
bit 1
FIFO valid data number
0 FIFO: number of valid Data Bit 1
bit 2
FIFO valid data number
0 FIFO: number of valid Data Bit 2
bit 3
FIFO valid data number
0 FIFO: number of valid Data Bit 3
bit 4
FIFO valid data number
0 FIFO: number of valid Data Bit 4
bit 5
not used / always read 0
bit 6
not used / always read 0
bit 7
not used / always read 0
:
R : Flag is read only, writing to it
has no effect
: Initial value