FUJITSU MB91460 SERIES FR60 - Manual (Page 224)

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Chapter 14 PLL Interface
4.Registers
4. Registers
4.1 PLL Control Registers
Controls the PLL multiplier ratio (divide-by-M and divide-by-N) and the automatic clock gear up/down function.
• PLLDIVM: Address 048Ch (Access: Byte, Halfword, Word)
(See “ Meaning of Bit Attribute Symbols (Page No.10) ” for details of the attributes.)
• Bit7-4: Reserved bits. Always write “0” to these bits.
• Bit3-0: PLL divide-by-M selection
(Note) Even though it is possible to select no division ratio (:1) for the divide-by-M counter it is not
recommended. The resulting output clock will have an odd clock duty ratio (direct PLL output).
Always select at least a division ratio > 1 and an even division ratio (:2, :4, :6, etc.).
(Note) Even though it is possible to select an odd division ratio (:3, :5, :7, etc.) for the divide-by-M counter it
is not recommended. The resulting output clock will have an odd clock duty ratio. Always select an
even division ratio (:2, :4, :6, etc.).
(Note) The register value can not be changed once PLL is selected as clock source (CLKS[1:0]=”10”).
(Note) It is strongly recommended to disable the PLL (CLKR.PLL1EN=0) while or after changing the
PLLDIVM and PLLDIVN registers and to enable the PLL (CLKR.PLL1EN=1) afterwards.
• PLLDIVN: Address 048Dh (Access: Byte, Halfword, Word)
7 6 5 4 3 2 1 0 bit
- - - - DVM3 DVM2 DVM1 DVM0
0 0 0 0 0 0 0 0
Initial value ( INIT pin input,
watchdog reset )
0 0 0 0 X X X X
Initial value
(Software reset)
R0/W0 R0/W0 R0/W0 R0/W0 R/W R/W R/W R/W Attribute
DVM3-DVM0 PLL output divided-by-M (generates Φ : Base clock)
0000 Source (F
CL-PLL
)
: 1 (no division)
0001 Source (F
CL-PLL
)
: 2 (division by 2)
0010 Source (F
CL-PLL
)
: 3 (division by 3)
0011 Source (F
CL-PLL
)
: 4 (division by 4)
0100 Source (F
CL-PLL
)
: 5 (division by 5)
0101 Source (F
CL-PLL
)
: 6 (division by 6)
0110 Source (F
CL-PLL
)
: 7 (division by 7)
0111 Source (F
CL-PLL
)
: 8 (division by 8)
...... .....
1111 Source (F
CL-PLL
)
: 16 (division by 16)
7 6 5 4 3 2 1 0 bit
- - DVN5 DVN4 DVN3 DVN2 DVN1 DVN0
0 0 0 0 0 0 0 0
Initial value ( INIT pin input,
watchdog reset )
0 0 X X X X X X
Initial value
(Software reset)
R0/WX R0/WX R/W R/W R/W R/W R/W R/W Attribute