FUJITSU MB91460 SERIES FR60 - Manual (Page 559)

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Chapter 31 External Bus
4.Endian and Bus Access
4. Endian and Bus Access
There is a one-to-one correspondence between the WR0-WR3 control signal and the byte loca-
tion regardless of the endian method (big or little) and the data bus width. The following sum-
marizes the location of bytes on the data bus of the MB91460 series used according to the
specified data bus width and the corresponding control signal for each bus mode.
■
Relationship between Data Bus Width and Control Signal
This section summarizes the location of bytes on the data bus used according to the specified data bus width and
the corresponding control signal for each bus mode.
●
Ordinary bus interface
Figure 4-1 Data Bus Width and Control Signal on the Ordinary Bus Interface
●
Time division I/O interface
Figure 4-2 Data Bus Width and Control Signal in the Time Division I/O Interface
D31
D0
a) 32-bit bus width
data bus Control signal
WR0
(UUB)
WR1
(ULB)
WR2
(LUB)
WR3
data bus Control signal data bus Control signal
WR0
(UUB)
WR1
(ULB)
WR0
(UUB)
-
-
-
-
-
b) 16-bit bus width c) 8-bit bus width
(D15 to 0 are not used) (D23 to 0 are not used)
-
-
-
-
-
(LLB)
WR0
WR1
WR0
(D15 to 0 are not used) (D23 to 0 are not used)
-
-
A15 to 8
A7 to 0 -
-
-
A7 to 0
-
-
-
-
-
-
-
- -
-
D31
D16
data bus Control signal data bus Control signal
a) 16-bit bus width b) 8-bit bus width