FUJITSU MB91460 SERIES FR60 - Manual (Page 141)

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Chapter 6 EIT: Exceptions, Interrupts and Traps
8.Operation
8. Operation
In the following sections, note that source “PC” means instruction address which detected each EIT trigger.
Similarly, “address of next instruction” means the following addresses based on the instruction which detected
the EIT.
• When LDI is 32: PC+6
• When LDI is 20, and it is COPOP, COPLD, COPST or COPSV: PC+4
• For other instructions: PC+2
8.1 User Interrupt operation
If user interrupt request occurs, it determines whether to receive its request or not in the following sequence.
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How to determine whether to receive interrupt request or not
1. Selects the interrupt which holds the highest priority level (the smallest number) by comparing interrupt
request levels generated at the same time.
For the level to be compared, it uses the value which ICR holds corresponding to maskable interrupt.
2. Selects the interrupt request which has the earliest interrupt number if multiple interrupt requests with the
same priority level are generated.
3. Where “Interrupt level Level mask value”, the interrupt request is masked without receipt. Where
“Interrupt level < Level mask value”, it goes forward to Step 4.
4. When selected interrupt request is maskable interrupt, if I flag is 0, its Interrupt request is masked without
receipt and if I flag is 1, it goes forward to Step 5.
5. If conditions above are satisfied, interrupt requests are received between instruction processes.
If user interrupt requests are received upon detecting EIT requests, CPU executes the following operations
according to the Interrupt number for the interrupt request received.
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Operation
1. The contents of the program status (PS) are saved to the system stack.
2. The address of the next instruction is saved to the system stack.
3. The value of the system stack pointer (SSP) is reduced by 8.
4. The value (level) of the accepted interrupt is stored in the “ILM”.
5. The value “0” is written to the “S” flag in the condition code register (CCR) in the program status (PS).
6. The vector address of the accepted interrupt is stored in the program counter (PC).
After the interrupt sequence, EIT is checked again before executing the main program handler’s instruction. If
any receivable EIT is generated at this time, the CPU goes to EIT process sequence.
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