FUJITSU MB91460 SERIES FR60 - Manual (Page 299)

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Chapter 21 Hardware Watchdog Timer
1.Overview
Chapter 21 Hardware Watchdog Timer
1. Overview
The hardware watchdog timer (R/C oscillation based) provides a system reset if an internal
watchdog timer is not cleared within the postponement duration.
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Hardware watchdog timer
This watchdog timer starts counting after the setting initialization reset (INIT) automatically. Clearing the
counter in the postponement duration is necessary to continue running an application. Otherwise if the counter
is not cleared within the postponement duration, e.g. due to infinite loop in the application, this module
provides a reset signal (initialisation reset, INIT), which width is typical 20us (2 RC clock cycles at typical
100kHz).
If the CPU is in a standby mode as described below, this watchdog timer stops:
• SLEEP mode: the CPU stops, the peripherals run.
• STOP mode: the CPU and the peripherals stop.
• RTC mode: the CPU and the peripherals stop but the RTC module and the oscillator run.
If one of the below condition occurs, the watchdog counter is cleared:
• Writing “0” to CL bit in the HWWD register
• Initialisation Reset (INIT)
• Operational Reset (RST)
• Oscillation stops
• Transition to the SLEEP/RTC/STOP mode