FUJITSU MB91460 SERIES FR60 - Manual (Page 227)

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Chapter 14 PLL Interface
4.Registers
• While switching from clock source PLL to clock source oscillator this flag is set when the divide-by-G
counter reaches the programmed end value.
• This bit is read as “1” at a Read-Modify-Write instructions. Writing “1” has no effect.
• Bit1: Interrupt Enable Gear UP.
• Bit2: Interrupt Flag Gear UP.
• While switching from clock source oscillator to clock source PLL this flag is set when the divide-by-G
counter reaches the end value defined by the divide-by-M counter.
• This bit is read as “1” at a Read-Modify-Write instructions. Writing “1” has no effect.
IEUP Function
0 Gear UP interrupt disabled [Initial value]
1 Gear UP interrupt enabled
GRUP Function
0 Gear UP interrupt not active [Initial value]
1 Gear UP interrupt active