Document Outline

• Title Page
• Contents
• Revision History
• Introduction
  • About This Design Guide
  • Reference Documents
  • System Overview
    • Chipset Components
    • Bandwidth Summary
    • System Configuration
  • Platform Initiatives
    • Direct Rambus RAM (RDRAM*)
    • Streaming SIMD Extensions
    • AGP 2.0.
    • Hub Interface
    • Integrated LAN Controller
    • Ultra ATA/100 Support
    • Expanded USB Support
    • Manageability
    • AC’97
    • Low-Pin-Count (LPC) Interface
• Layout/Routing Guidelines
  • General Recommendations
  • Component Quadrant Layout
  • Intel® 820E Chipset Component Placement
  • Core Chipset Routing Recommendations
  • Source-Synchronous Strobing
  • Differential Clocking/Strobing
  • Direct RDRAM* Interface
    • Stack-Up
    • Direct RDRAM* Layout Guidelines
      • RSL Routing
      • RSL Termination
      • Direct RDRAM* Ground Plane Reference
      • Direct RDRAM* Connector Compensation
        • Direct RDRAM* Channel Connector Compensation Enhancement Recommendation
      • RSL Signal Layer Alternation
      • Length Matching Methods
      • Via Compensation
      • Length Matching and Via Compensation Example
    • Direct RDRAM* Reference Voltage
    • High-Speed CMOS Routing
      • SIO Routing
      • Suspend-to-RAM Shunt Transistor
    • Direct RDRAM* Clock Routing
    • Direct RDRAM* Design Checklist
  • AGP 2.0
    • AGP Interface Signal Groups
    • 1× Timing Domain Routing Guidelines
    • 2Ч/4Ч Timing Domain Routing Guidelines
    • AGP 2.0 Routing Summary
    • AGP Clock Routing
    • General AGP Routing Guidelines
      • Recommendations
    • VDDQ Generation and TYPEDET#
    • VREF Generation for AGP 2.0 (2× and 4×)
    • Compensation
    • AGP Pull-Ups
      • AGP Signal Voltage Tolerance List
    • Motherboard / Add-in Card Interoperability
    • AGP Universal Retention Mechanism (RM)
  • Hub Interface
    • 8-Bit Hub Interface Routing Guidelines
      • 8-Bit Hub Interface Data Signals
      • 8-Bit Hub Interface Strobe Signals
      • 8-Bit Hub Interface HUBREF Generation/Distribution
      • 8-Bit Hub Interface Compensation
      • 8-Bit Hub Interface Decoupling Guidelines
  • System Bus Design – Pentium® III Processor for the Intel® PGA370 Socket Layout Guidelines
    • System Bus Ground Plane Reference
  • Additional Host Bus Guidelines
  • IDE Interface
    • Cable Detection for Ultra ATA/66 and Ultra ATA/100
    • Combination Host-Side/Device-Side Cable Detection
    • Device-Side Cable Detection
    • Primary IDE Connector Requirements
    • Secondary IDE Connector Requirements
  • AC’97
    • AC’97 Audio Codec Detect Circuit and Configuration Options
    • Communication and Networking Riser (CNR)
    • AC’97 Routing
    • Motherboard Implementation
  • USB
    • Using Native USB Interface
    • Disabling the Native USB Interface of ICH2
  • ISA Support
  • I/O APIC Design Recommendation
  • SMBus/SMLink Interface
  • PCI
  • RTC
    • RTC Crystal
    • External Capacitors
    • RTC Layout Considerations
    • RTC External Battery Connection
    • RTC External RTCRST Circuit
    • RTC Routing Guidelines
    • VBIAS DC Voltage and Noise Measurements
    • RTC-Well Input Strap Requirements
  • SPKR Pin Consideration
  • ICH2 PIRQ Routing
  • LAN Layout Guidelines
    • ICH2 – LAN Interconnect Guidelines
      • Bus Topologies
      • Point-to-Point Interconnect
      • LOM/CNR Interconnect
      • Signal Routing and Layout
      • Crosstalk Consideration
      • Impedances
      • Line Termination
    • General LAN Routing Guidelines and Considerations
      • General Trace Routing Considerations
        • Trace Geometry and Length
        • Signal Isolation
      • Power and Ground Connections
        • General Power and Ground Plane Considerations
      • 4-Layer Board Design
        • • Top-Layer Routing
          • Ground Plane
          • Power Plane
          • Bottom Layer Routing
          • Common Physical Layout Issues
    • Intel® 82562EH Home/PNA* Guidelines
      • Power and Ground Connections
      • Guidelines for Intel® 82562EH Component Placement
      • Crystals and Oscillators
      • Phoneline HPNA Termination
      • Critical Dimensions
        • Distance from Magnetics Module to Line RJ11
        • Distance from Intel® 82562EH Component to Magnetics Module
        • Distance from LPF to Phone RJ11
    • Intel® 82562ET / Intel® 82562EM Component Guidelines
      • Guidelines for Intel® 82562ET / Intel® 82562EM Component Placement
      • Crystals and Oscillators
      • Intel® 82562ET / Intel® 82562EM Component Termination Resistors
      • Critical Dimensions
        • Distance from Magnetics Module to RJ45
        • Distance from the Intel® 82562ET Component to the Magnetics Module
      • Reducing Circuit Inductance
      • Terminating Unused Connections
        • Termination Plane Capacitance
    • Intel® 82562ET/EM Disable Guidelines
    • Intel® 82562ET and Intel® 82562EH Components’ Dual-Footprint Guidelines
    • ICH2 Decoupling Recommendations
  • FWH Flash BIOS Guidelines
    • In-Circuit FWH Flash BIOS Programming
    • FWH Flash BIOS VPP Design Guidelines
  • ICH2 Design Checklist
  • ICH2 Layout Checklist
• Advanced System Bus Design
  • Terminology and Definitions
    • Initial Timing Analysis
    • Determine the Desired General Topology, Layout, and Routing
    • Pre-Layout Simulation
      • Methodology
      • Sensitivity Analysis
      • Monte Carlo Analysis
      • Simulation Criteria
    • Place and Route Board
      • Estimate Component-to-Component Spacing for AGTL+ Signals
      • Layout and Route Board
      • Host Clock Routing
      • APIC Data Bus Routing
    • Post-Layout Simulation
      • Intersymbol Interference
      • Crosstalk Analysis
      • Monte Carlo Analysis
    • Validation
      • Measurements
      • Flight Time Simulation
      • Flight Time Hardware Validation
  • Theory
    • AGTL+
    • Timing Requirements
    • Crosstalk Theory
      • Potential Termination Crosstalk Problems
  • More Details and Insight
    • Textbook Timing Equations
    • Effective Impedance and Tolerance/Variation
    • Power/Reference Planes, PCB Stack-Up, and High-Frequency Decoupling
      • Power Distribution
      • Reference Planes and PCB Stack-Up
      • High-Frequency Decoupling
    • Clock Routing
  • Definitions of Flight Time Measurements/Corrections and Signal Quality
    • VREF Guard Band
    • Ringback Levels
    • Overdrive Region
    • Flight Time Definition and Measurement
  • Conclusion
• Clocking
  • Clock Generation
  • Component Placement and Interconnection Layout Requirements
    • 14.318 MHz Crystal to CK133
    • CK133 to DRCG
    • MCH to DRCG
    • DRCG-to-RDRAM Channel
    • Trace Length
  • DRCG Impedance Matching Circuit
    • DRCG Layout Example
  • AGP Clock Routing Guidelines
  • Clock Routing Guidelines for Intel® PGA370 Designs
  • Series Termination Resistors for CK133 Clock Outputs
  • Unused Outputs
  • Decoupling Recommendation for CK133 and DRCG
  • DRCG Frequency Selection and the DRCG+
    • DRCG Frequency Selection Table and Jitter Specification
    • DRCG+ Frequency Selection Schematic
• System Manufacturing
  • Stack-Up Requirement
    • PCB Materials
    • Design Process
    • Test Coupon Design Guidelines
    • Recommended Stack-Up
    • Inner-Layer Routing
    • Impedance Calculation Tools
    • Testing Board Impedance
    • Board Impedance/Stack-up Summary
• System Design Considerations
  • Power Delivery
    • Terminology and Definitions
    • ICH2 1.8 V / 3.3 V Power Sequencing
    • Excessive Power Consumption by 64/72-Mbit RDRAM
      • Option 1: Reduce the Clock Frequency During Initialization
      • Option 2: Increase the Current Capability of the 2.5 V Voltage Regulator
  • ICH2 Power Plane Split
  • Thermal Design Power
  • Glue Chip 3 (Intel® 820E Chipset Glue Chip)
• Appendix A: Reference Design Schematics (Uniprocessor)