Intel CHIPSET 820E - Manual (Page 101)

Intel ® 820E Chipset
R
Design Guide 101
logic low. When the jumper is not populated, a low can still be read on the signal line if the effective
impedance due to the speaker and codec circuit is equal to or less than that of the integrated pull-up
resistor. Therefore, it is strongly recommended that the effective impedance be greater than 50 k
Ω and
the pull-down resistor be less than 7.3 k Ω .
Figure 62. SPKR Circuit
ICH2
Integrated pull-up
18–42 k Ω
3.3 V
SPKR
Stuff jumper to
disable timeout
feature.
R < 7.3 k
Ω
Effective impedance
due to speaker and
codec circuit
R
EFF
> 50 k Ω
spkr_circ
It should be noted that this is not the only solution to this problem. Board designers can also isolate the
load from the SPKR pin until POWEROK is in a stable high state. This would allow a weak effective
load to be implemented.
2.21. ICH2 PIRQ Routing
This section deals with the routing of the four added PCI IRQ signals implemented with the ICH2.
The PCI interrupt request signals E-H are new to the ICH2. These signals have been added to lower the
latency caused by the presence of multiple devices on one interrupt line. These new signals allow each
PCI slot to have an individual PCI interrupt request line, assuming that the system has four PCI slots. The
following table shows how the ICH2 uses the PCI IRQ when the I/O APIC is active.
Table 21. Usage of I/O APIC Interrupt Inputs 16 through 23
No. IOAPIC INTIN PIN Function in ICH2 using the PCI IRQ in IOAPIC
1 IOAPIC INTIN PIN 16 (PIRQA)
2 IOAPIC INTIN PIN 17 (PIRQB) AC’97, modem and SMBUS
3 IOAPIC INTIN PIN 18 (PIRQC)
4 IOAPIC INTIN PIN 19 (PIRQD) USB controller 1
5 IOAPIC INTIN PIN 20 (PIRQE) Internal LAN device
6 IOAPIC INTIN PIN 21 (PIRQF)
7 IOAPIC INTIN PIN 22 (PIRQG)
8 IOAPIC INTIN PIN 23 (PIRQH) USB controller 2