Intel CHIPSET 820E - Manual (Page 139)

Intel ® 820E Chipset
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Design Guide 139
3. Advanced System Bus Design
Section 2.10 describes the recommendations for designing Intel 820E chipset-based platforms. This
section discusses in more detail the methodology used to develop the advanced system bus guidelines.
These layout considerations apply to Intel 820E chipset/FC-PGA designs. The design guidelines for the
Pentium
® III processor for the Intel PGA370 socket are found in the Intel ® 820 Platform Design Guide
Addendum, Revision 0.95.
Section 3.2 discusses specific system guidelines. This is a step-by-step methodology that Intel has
successfully used to design high-performance desktop systems. Section 3.3 introduces the theories
applicable to this layout guideline. Section 3.4 contains more details and insights. Section 3.4 expands on
part of the rationale for the recommendations in the step-by-step methodology. This section also includes
equations that may be used for reference.
3.1. Terminology and Definitions
Term Definition
Aggressor The network that transmits a coupled signal to another network is called the
aggressor network.
AGTL+ The processor system bus uses a bus technology called AGTL+ (Assisted Gunning
Transceiver Logic). AGTL+ buffers are open-drain and require pull-up resistors for
providing the high logic level and termination. The processor’s AGTL+ output
buffers differ from the GTL+ buffers, with the addition of an active pMOS pull-up
transistor to “assist” the pull-up resistors during the first clock of a low-to-high
voltage transition.
Bus agent Component or group of components that, when combined, represent a single load
on the AGTL+ bus
Corner Describes how a component performs when all parameters that could affect
performance are adjusted to have the same effect on performance. Examples of
these parameters include variations in the manufacturing process, the operating
temperature, and the operating voltage. The resulting performance of an electronic
component that may change as a result of corners includes, but is not limited to, the
following: clock-to-output time, output driver edge rate, output drive current, and
input drive current. A “slow” corner means a component operating at its slowest,
weakest drive strength performance. Conversely, a “fast” corner means a
component operating at its fastest, strongest drive strength performance. Operation
or simulation of a component at its slow and fast corners should bound the
extremes between slowest, weakest performance and fastest, strongest performance.
Crosstalk The reception on a victim network of a signal imposed by an aggressor network(s),
through inductive and capacitive coupling between the networks
Backward crosstalk: Coupling that creates a signal in a victim network, that travels
in the direction opposite to the aggressor’s signal
Forward crosstalk: Coupling that creates a signal in a victim network, that travels in
the same direction as the aggressor’s signal
Even-mode crosstalk: Coupling from multiple aggressors when all aggressors
switch in the direction in which the victim is switching
Odd-mode crosstalk: Coupling from multiple aggressors when all aggressors switch
in the direction opposite to that in which the victim is switching