Intel CHIPSET 820E - Manual (Page 148)

Intel ® 820E Chipset
R
148 Design Guide
AGTL+. Intragroup AGTL+ crosstalk involves interference between AGTL+ signals within the same
group. (See Section 3.4 for a description of the different AGTL+ group types.) Intergroup AGTL+
crosstalk involves the interference of AGTL+ signals in a particular group with AGTL+ signals in a
different group. An example of AGTL+-to-non-AGTL+ crosstalk is when CMOS and AGTL+ signals
interfere with each other.
Table 54. Trace Width Space Guidelines
Crosstalk Type Trace Width:Space Ratio
Intragroup AGTL+ (same group AGTL+) 5:10 or 6:12
Intergroup AGTL+ (different group AGTL+) 5:15 or 6:18
AGTL+ to non-AGTL+ 5:20 or 6:24
The spacing between the various bus agents causes variations in trunk impedance and stub locations.
These variations cause reflections that can cause constructive or destructive interference at the receivers.
Noise may be reduced by providing minimal spacing the agents. Unfortunately, tighter spacing results in
reduced component placement options and lower hold margins. Therefore, adjusting the inter-agent
spacing may be one way to change the network’s noise margin, but mechanical constraints often limit the
usefulness of this technique. Always be sure to validate signal quality after making any changes in agent
locations or changes to inter-agent spacing.
Six AGTL+ signals can be driven simultaneously by more than one agent. These signals may require
more attention during the layout and validation portions of the design. When a signal is asserted (i.e.,
driven low) by two or more agents on the same clock edge, the two falling-edge wavefronts will meet at
some point on the bus and can sum to form a negative voltage. The ringback from this negative voltage
can easily cross into the overdrive region. The signals are AERR#, BERR#, BINIT#, BNR#, HIT#, and
HITM#.
This document addresses AGTL+ layout for both one-way and two-way 133 MHz/100 MHz processor/
Intel 820E chipset systems. Power distribution and chassis requirements for cooling, connector location,
memory location, etc., may constrain the system topology and component placement location, thereby
constraining the board routing. These issues are not addressed directly in this document. Section 1.2
contains a listing of several documents that address some of these issues.
3.2.4.3. Host Clock Routing
For Intel 820E chipset/FC-PGA clock routing guidelines, refer to the Intel ® 820 Chipset Design Guide
Addendum for the Intel ® Pentium ® III Processor for the PGA370 Socket. These guidelines can be
downloaded from the Intel website at http://developer.intel.com/design/chipsets/designex/298178.htm .
3.2.4.4. APIC Data Bus Routing
Intel recommends using the in-line topology shown in the following two figures for the APIC data
signals, PICD[1:0]. For dual-processor systems, the network should be dual-end terminated with 300
Ω
to 330 Ω resistors. For Intel 820E chipset/FC-PGA APIC (PICD[1:0]) routing guidelines, refer to the
Intel ® 820 Chipset Design Guide Addendum for the Intel ® Pentium ® III Processor for the PGA370
Socket. These guidelines can be downloaded from the Intel website at
http://developer.intel.com/design/chipsets/designex/298178.htm .