Intel CHIPSET 820E - Manual (Page 122)

Intel ® 820E Chipset
R
122 Design Guide
• Traces from magnetics to connector must be shared and not stubbed. An RJ-11 connector that fits
into the RJ-45 slot is available. Any amount of stubbing will destroy both HomePNA* and Ethernet
performance.
2.22.7. ICH2 Decoupling Recommendations
The ICH2 can generate large current swings when switching between logic high and logic low. This
condition could cause the component voltage rails to drop below the specified limits. To avoid such a
situation, ensure that the appropriate amount of bulk capacitance is added in parallel with the voltage
input pins. It is recommended that the developer use the number of decoupling capacitors specified in the
following table, to ensure that the component maintains stable supply voltages. The capacitors should be
placed as close as possible to the package. Refer to Figure 78 for a layout example. For prototype board
designs, it is recommended that the designer include pads for extra power plane decoupling caps.
Table 25. Decoupling Capacitor Recommendation
Power Plane/Pins # Decoupling
Capacitors
Capacitor Value
(µF)
3.3 V core 6 0.1
3.3 V standby 1 0.1
processor I/F (1.3 – 2.5 V) 1 0.1
1.8 V core 2 0.1
1.8 V standby 1 0.1
5 V reference 1 0.1
5 V reference standby 1 0.1