Hub in ter fa ce connector for debug only – Intel CHIPSET 820E User Manual

Page 239

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43

TEST_CLK66

5

HL7

7,8

HL6

7,8

HL5

7,8

HL4

7,8

HL8

7,8

HL10

7,8

HL_STB#

7,8

HL_STB

7,8

HL9

7,8

HL3

7,8

HL2

7,8

HL1

7,8

HL0

7,8

6,8

HUBREF

J26

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1

DRAWN BY:

LAST REVISED:

SHEET:

FOLSOM, CALIFORNIA 95630

1900 PRAIRIE CITY ROAD

87

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1

A

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PCG PLATFORM DESIGN

REV:

0.5

PROJECT:

OF 40

TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD

R

PCG AE

Camino2

VCC1_8

P08-050-SL-A-G

PROBE CONNECTOR

Hub

In

ter

fa

ce

Connector

For debug only.

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