Intel CHIPSET 820E - Manual (Page 41)

Intel ® 820E Chipset
R
Design Guide 41
All four layers of the motherboard require correct grounding between the RSL signals on the
motherboard, as follows:
• Layer 1 = Ground isolation
• Layer 2 = Ground plane
• Layer 3 = Ground reference in the power plane
• Layer 4 = Ground isolation
All ground vias and pins MUST be connected to all 4 layers.
2.7.2.4. Direct RDRAM* Connector Compensation
The RIMM connector inductance causes an impedance discontinuity on the Direct RDRAM channel.
This may reduce the voltage and timing margin.
To compensate for the inductance of the connector, an approximately 0.65 pF to 0.85 pF compensating
capacitive tab (C-TAB) is required on each RSL connector pin. This compensating capacitance must be
added to the following connector pins at each connector:
LCTM LCTM#
RCTM RCTM#
LCFM LCFM#
RCFM RCFM#
LROW[2:0] RROW[2:0]
LCOL[4:0] RCOL[4:0]
RDQA[8:0] LDQA[8:0]
RDQB[8:0] LDQB[8:0]
SCK CMD
This can be achieved on the motherboard by adding a copper tab to the specified RSL pins at each
connector. The target value is approximately 0.65 pF – 0.85 pF. The copper tab area for the
recommended stack-up was determined by means of simulation. The copper tabs can be placed on any
signal layer, independently of the layer on which the RSL signal is routed.
The following equation is an approximation usable for calculating the copper tab area on an outer layer.
Equation 1. Approximate Copper Tab Area Calculation
Length × Width = Area = C
PLATE
× Thickness of prepreg / [( ε
0
) ( ε
r
) (1.1)]
Where:
 ε
0
= 2.25 × 10 -16 Farads/mil
 ε
r
= Relative dielectric constant of prepreg material
 Thickness of prepreg (stack-up dependent)
 Length, Width = Dimensions (in mils) of copper plate to be added
 Factor of 1.1 accounts for fringe capacitance.
Based on the stack-up requirement in Section 5.1, the copper tab area should be 2800 to 3600 square
mils. Different stack-ups require different copper tab areas. The following table
lists example copper tab
areas.