Ich 2, Ich2 – Intel CHIPSET 820E User Manual
Page 204
3-20-2000_14:02
8
ICH2
ICH_HLCOMP
GPIO18
VDDQ
VCC3_3
VCC1_8SBY
VCC2_5SBY
VCC2_5
4,6,37
CPURST#
9,36
RSMRST#
9,35
SLP_S5#
6,8,10,11,12,24,25,26,27
PCIRST#
4,8,36
PWRGOOD
4,8,36
PWRGOOD
GPIO12
GPIO8
12,38
A20GATE
4
A20M#
4
CPUSLP#
4,38
FERR#
4
IGNNE#
4,10
HINIT#
4
LINT0
4
LINT1
4
SMI#
4
STPCLK#
12,38
KBRST#
GPIO20
GPIO19
GPIO7
ICHPCLK
5
7
HL[10:0]
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
7
HL_STB
7
HL_STB#
25,26,38
PERR#
25,26,38
SERR#
25,26,38
PLOCK#
25,26,38
STOP#
25,26,38
TRDY#
25,26,38
IRDY#
25,26,38
FRAME#
25,26,38
DEVSEL#
25,26
AD[31:0]
AD31
AD18
AD19
AD20
AD22
AD21
AD23
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7 AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD24
AD25
AD26
AD27
AD28
AD29
AD30
27,38
IRQ14
27,38
IRQ15
5
APICCLK_ICH
4,38
APICD0
25,38
PGNT#0
25,38
PGNT#1
26,38
PGNT#2
38
PGNT#3
38
PGNT#4
26
PGNT#5
16
LAN_TXD2_ICH2
16
LAN_CLK_ICH2
16
LAN_RST_ICH2
J17
28
27
25
26
9
8
7
6
5
4
3
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
R10
330
1%
R5
330
TP4
TP3
R16
301-1%
R19
301-1%
0.1UF
C31
0.01UF
C5
R15
40.2-1%
CR3
1
2
TP1
8.2K
R6
HL11_TP
25,26,38
PIRQ#C
25,26,38
PIRQ#D
24,25,26,38
PIRQ#B
24,25,26,38
PIRQ#A
12,26,38
SERIRQ
4,38
APICD1
25,38
PREQ#0
38
PREQ#3
38
PREQ#4
26,38
PREQ#5
26,38
PREQ#2
25,38
PREQ#1
9,34,36
SLP_S3#
7,9,34,36
PWROK
4,9,33,36
VRM_PWRGD
VCC3_3SBY
6,8,10,11,12,24,25,26,27
PCIRST#
25,26
PAR
25,26
C_BE#0
25,26
C_BE#1
25,26
C_BE#2
25,26
C_BE#[3:0]
25,26
C_BE#3
5
MULT0_GPIO
DRCG_CTRL
5
8.2K
R11
24,25,26
PCI_PME#
R14
10K
26
GNT#A
GPIO4
PIRQE#
GPIO3
6,8
HUBREF
6,8
HUBREF
16
LAN_RXD0_ICH2
16
LAN_TXD0_ICH2
16
LAN_RXD1_ICH2
16
LAN_RXD2_ICH2
16
LAN_TXD1_ICH2
U13
P3
W2
H2
R3
C16
F21
L4
L2
L3
A13
C13
W5
W4
AB8
U4
F3
G2
AA14
D14
W11
A7
A6
W14
A15
AB15
N1
N2
N3
A3
W7
Y7
C6
B6
B5
A4
A5
C10
B11
D11
A12
R22
A11
C12
B12
B13
P1
P2
N4
R2
T1
AB10
P4
M2
M1
R4
T2
R1
M3
Y15
AA7
AA15
W1
V4
W8
V3
AB7
AA9
Y8
AB6
AA3
Y2
C8
A9
B8
A8
AA5
AB3
Y5
Y4
AB4
AA4
B4
T4
W9
T3
AA10
C5
C7
C11
AA8
V1
W10
Y9
U2
U3
W3
AB9
U1
V2
AA6
Y1
W6
Y3
AB5
Y6
B7
Y10
Y14
AA11
N20
P22
N19
N21
L1
A14
B14
C14
AB14
G1
H1
F2
F1
G3
15
PRIMARY_DN#
VCC3_3
DRAWN BY:
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE
Camino2
VCC1_8
VCC1_8
VCC1_8
VCC2_5
CPU
HUB
IRQ
PCI
ICH2
VC
C3_3;
E14,
E15,
E16,
E17,
E18,
F18,G
18,H
18,J18
VC
C3_3;
P18,
R18,
R5
,T
5,U
5,V
5,V
6,V
7,V
8
GPIO
PCI
LAN
GN
D;E
6,E
7,E
8,E
9,J10,
J11,J12,
J13,J14,
J9,K
1,K
10,K
11,K
12,K
13,K
14
GN
D;K
9,L10,
L11,L12,
L13,L14,
L9,M
10,M
11,M
12,M
13,M
14,M
9,N
10
VC
C1_8;
D10,
D2
,E
5,K
19,L19,
P5
,V
9
GN
D;A
1,A
10,A
2,A
21,A
22,B
1,B
10,B
2,B
3,B
21,B
22,B
9,C
2,C
3,C
4,C
9,D
3,D
5,D
6,D
7,D
8,D
9
GN
D;N
11,N
12,N
13,N
14,N
9,P
10,P
11,P
12,P
13,P
14,P
9,A
A1
,A
A2
,A
A21,
AA
22,A
B1
,A
B2
,A
B21,
AB
22
LAN_CLK
LAN_TXD2
LAN_TXD1
LAN_RXD2
LAN_RXD1
GPIO27
GPIO20
GPIO22
GPIO23
GPIO21
SERIRQ
APICD1
APICD0
APICCLK
GPIO7
GPIO8
AD29
HL4
AD12
AD8
AD9
AD10
AD15
AD14
AD16
AD26
AD25
AD11
AD22
AD24
AD23
AD27
AD18
AD17
INTR
HL10
HL11
AD31
AD30
AD21
AD28
HUBREF
AD0
AD1
AD2
AD5
AD6
AD7
HL5
HL6
HL7
HL8
AD13
C/BE#0
C/BE#1
C/BE#2
C/BE#3
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PCIRST#
PLOCK#
PME#
GPIO0/REQA#
GNT#4
GNT#3
GNT#2
GNT#1
GNT#0
REQ#4
REQ#3
REQ#2
REQ#0
PIRQD#
PIRQB#
PIRQA#
RCIN#
SMI#
INIT#
IGNNE#
FERR#
CPUSLP#
A20M#
NMI
STPCLK#
HL2
HL0
HL1
HL3
HL9
PERR#
SERR#
HLCOMP
GPIO2/PIRQE#
GPIO3
GPIO4
GPIO13
GPIO18
GPIO12
HL_STB
HL_STB#
PCICLK
GPIO19
GPIO28
LAN_RXD0
LAN_TXD0
AD20
AD19
AD4
AD3
A20GATE
CPUPWRGD
GPIO1/REQB#/REQ5#
GPIO16/GNTA#
GPIO17/GNTB#/GNT5#
IRQ14
IRQ15
REQ#1
LAN_RSTSYNC
PAR
PIRQC#
Led Blink with GPIO
Place C237 close to ICH.
Place HUBREF circuit between MCH and ICH
HUBREF voltage = 0.9V +/- 2%
Test header. For debug only.
ICH 2
Place R138 less than 0.5" from the ICH using a 10 mil trace.