Intel CHIPSET 820E - Manual (Page 178)

Intel ® 820E Chipset
R
178 Design Guide
5.1.2. Design Process
To meet the tight tolerances required, a good design process is as follows:
• Specify the material to be used.
• Calculate the board geometries for the desired impedance or use the example stack-up provided.
• Build test boards and coupons.
• Measure the board impedance using a TDR and follow Intel’s Impedance Test Methodology
Document (located on the
developer.intel.com web site).
• Measure geometries with cross section.
• Adjust design parameters and/or material, as required.
• Build a new board and remeasure the key parameters. Be prepared to generate one or two board
iterations.
This process will require iteration, as follows: design, build, test, modify, build, test….
5.1.3. Test Coupon Design Guidelines
To deliver reliable systems at increased bus frequencies, it is critical to characterize and understand the
trace impedance. Incorporating a test coupon design into the motherboard makes testing simpler and
more accurate. The test coupon pattern must match the probe type being used.
The test coupon location is listed in order of preference, as follows:
• 1st choice (ideal location) = Memory section of the motherboard
• 2nd choice = Any section of the motherboard
• 3rd choice = Separate location in the panel
The Intel Printed Circuit Board (PCB) Test Methodology Document (order 298179) should be used to
ensure boards are within the 28
Ω ± 10% requirement. The Intel Controlled Impedance Design and Test
Document should be used for the test coupon design and implementation. These documents can be found
at:
http://developer.intel.com/design/chipsets/memory/rdram.htm (Select “Application Notes”.)