Intel CHIPSET 820E User Manual
Page 58
Intel
®
820E Chipset
R
58
Design
Guide
If any RSL signals are routed, even for a short distance, out of the last RIMM (towards
termination) on the bottom side, ensure that the ground reference plane (on the third layer) is
continuous under the termination resistors/capacitors.
Ensure that the current path for power delivery to the MCH does not go through the V
TERM
island.
•
CTM/CTM# routed properly
CTM/CTM# are routed differentially from DRCG to last RIMM.
CTM/CTM# are ground-isolated from DRCG to last RIMM.
CTM/CTM# are ground-referenced from DRCG to last RIMM.
Vias are placed in ground isolation and ground reference every 0.5 inch.
When CTM/CTM# serpentine together, they MUST maintain exactly 6 mils of spacing.
•
Clean DRCG power supply
The 3.3 V DRCG power flood on the top layer should connect to each high-frequency (0.1 µF)
capacitor, to the 10 µF bulk tantalum capacitor, and to the ferrite bead.
High-frequency (0.1 µF) capacitors are near the DRCG power pins, with one capacitor next to
each power pin.
10
µ
F bulk tantalum capacitor near DRCG connected directly to the 3.3 V DRCG power flood
on the top layer
The ferrite bead isolating the DRCG power flood from the 3.3 V main power also connects
directly to the 3.3 V DRCG power flood on the top layer.
Use 2 vias on the ground side of each.
•
Good DRCG output network layout
Series resistors (39
Ω
) should be very near CTM/CTM# pins.
Parallel resistors (51
Ω
) should be very near series resistors.
CTM/CTM# should be 18 mils wide, from the CTM/CTM# pins to the resistors.
CTM/CTM# should be 14-on-6 routed differentially as close as possible after the resistor
network.
When not 14 on 6, the clocks should be 18 mils wide.
Ensure that CTM/CTM# are ground-referenced and the ground reference is connected to the
ground plane every 0.5 inch to 1 inch.
Ensure that CTM/CTM# are ground-isolated and the ground isolation is connected to the
ground plane every 0.5 inch to 1 inch.
Ensure that 15 pF EMI capacitors to ground are removed. (The pads are not necessary, and
removing the pads provides more space for better placement of other components.)
Ensure the that 4 pF-EMI capacitor is implemented (but do not assemble the capacitor).
•
Good RSL transmission lines
RSL traces are 18 mils wide.
When RSL traces neck down to exit the MCH BGA, the minimum width is 15 mils and the
neckdown is no longer than 25 mils in length.
RSL traces do not neck down when routing into the RIMM connector.
If tight serpentining is necessary, 10 mil ground isolation must be between serpentine
segments. (i.e., an RSL signal cannot serpentine so tightly that the signal is adjacent to itself
with no ground isolation between the serpentines.)
RSL traces do not cross power plane splits. RSL signals also must not be routed next to a
power plane split. (For example, the RSL signals on the 4
th
layer cannot be routed directly
below the ground isolation split on the 3
rd
layer.)
At all times, uniform ground isolation flood is exactly 6 mils from the RSL signals.
ALL RSL, CMD/SCK, and CTM/CTM#/CFM/CFM# signals have CTABs on each RIMM
connector pin.