Intel CHIPSET 820E - Manual (Page 96)

Intel ® 820E Chipset
R
96 Design Guide
2.18. PCI
The ICH2 provides a PCI Bus interface that is compliant with the PCI Local Bus Specification, Revision
2.2. The implementation is optimized for high-performance data streaming when the ICH2 acts as either
the target or the initiator on the PCI bus. For more information on the PCI Bus interface, refer to the PCI
Local Bus Specification, Revision 2.2.
The ICH2 supports six PCI Bus masters, excluding the ICH2, by providing six REQ#/GNT# pairs. In
addition, the ICH2 supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI
REQ#/GNT# pair.
Figure 58. PCI Bus Layout Example
ICH2
PCI_bus_layout_ex
2.19. RTC
The ICH2 contains a real-time clock (RTC) with 256 bytes of battery-backed SRAM. The internal RTC
module provides two key functions: keeping the date and time and storing system data in its RAM when
the system is powered down.
This section will discuss the recommended hookup for the RTC circuit for the ICH2.
Note: This circuit is not the same as the circuit used for the PIIX4.