Intel CHIPSET 820E - Manual (Page 50)

Intel ® 820E Chipset
R
50 Design Guide
Figure 29. RSL Signal Layer Alternation
MCH
Signal on secondary side
Signal on primary side
Signal A
Signal B
Signal A
Signal B
rsl_sig-lay_alter.vsd
Route on EITHER layer.
Ground isolation is
REQUIRED!
Te
rm
Table 7. RSL Routing Layer Requirements
MCH to 1st RIMM 1st RIMM to 2nd RIMM
Method 1 Primary side Secondary side
Method 2 Secondary side Primary side
2.7.2.6. Length Matching Methods
To allow for greater routing flexibility, the RSL signals require pad-to-pin length matching between the
MCH and the first connector. If the trace lengths are matched between the balls of the MCH and the pin
of the RIMM connector, the length mismatch between the pad (on the die) and the ball has not been
taken into account. However, given the package dimension, which represents the length from the pad to
the ball, the routing can compensate for this package mismatch. Therefore, the board length mismatch
can be increased.
The RSL channel requires the matching of the trace lengths from pad to pin within ±10 mils.
Given the following definitions:
• Package dimension: Representation of length from pad to ball
• Board trace length: Trace length on board
• Nominal RSL length: Length to which all signals are matched. (Note: There is not necessarily a
trace that is exactly to nominal length, but all RSL signals must be matched to within ±10 mils of
the nominal length.) The nominal RSL length is an arbitrary length, within the limits of the routing
guidelines, to which all the RSL signals will be matched (within 10 mils).