System, Pwm1 tach2 pwm2 – Intel CHIPSET 820E User Manual
Page 219
3-20-2000_11:31
SYSTEM
23
2.2K
R103
JP1
GPIO23_FPLED
U14
14
7
5
6
U14
4
3
7
14
R253
330
IRRX
12
1M
R252
SP1
1
2
IDEACTS#
27
27
IDEACTP#
R345
10K
R344
10K
JP24
1
2
3
JP23
3
2
1
R326
4.7K
JP22
3
2
1
4.7K
R316
12
PWM1
R329
4.7K
IDE_ACTIVE
9
PWRBTN#
12
TACH2
R257
0K
82
R357
12
IRTX
J25
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
470
R356
R358
4.7K
KEYLOCK#
12
R355
220
CR7
2
1
IRTX_R
HDLED_R
PLED_R
PWRBTN_FP#
SBY_LED_CR
U19
8
9
7
14
U19
14
7
12
DUAL_COLOR
CR6
12
LED_PU0
LED_PU1
GPIO26_FPLED
330
R246
4.7K
R234
C267
1UF
470PF
C354
470PF
C355
R359
100K
0.1U
F
C327
C316
0.1U
F
C322
0.1U
F
C350
0.1U
F
50V
2
1
C356
10UF
16V
1
2
12
PWM2
SW1
SPKR_ONBOARD
10K
R354
R289
330
2.2K
R98
R100
2.2K
U26
4
5
6
1
2
3
Q15
2
3
1
R101
2.2K
13
AC97_SPKR
9
SPKR
DRAWN BY:
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE
Camino2
SN74LVC07A
GND
VCC
VCC3_3SBY
VCC3_3SBY
SN74LVC07A
GND
VCC
VCC3_3
VCC3_3SBY
VCC5
VCC3_3SBY
VCC3_3
VCC3_3
NEG
POS
+
VCC5
VCC5
VCC12
VCC12
VCC12
VCC3_3
FNT_PNL_CONN
VCC3_3
VCC5
VCC3_3
SN74LVC07A
GND
VCC
VCC3_3SBY
SN74LVC07A
GND
VCC
VCC3_3SBY
+
+
C2
B1
E1
C1
B2
E2
FFB3904
IR
L2203NS
1
3
2
VCC3_3
VCC3_3
KEY
KEY
No stuff.
For test only
No stuff.
KEY
INFRARED
H.D. LED
PWM1
TACH2
PWM2
SPEAKER
POWER SW.
For test only
ICH
has internal pullup and debounce on PWRBTN#
KEY
KEY
KEY
KEYLOCK
POWER LED
Onboard LED indicates the standby well is on
PWM outputs from SIO need power buffers for driving fan inputs.
to prevent hot swapping memory.
For debug only.
System